Selective Wordline Driver Powering for SRAM Leakage Reduction
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Solution Overview
Problem
Current memory devices face significant power consumption issues due to leakage energy, particularly in SRAM arrays, which account for a substantial portion of the energy used in cache memories, and existing power-saving methods add complexity and overhead.
Innovation Solution
A method and apparatus that selectively power individual wordline drivers in memory devices based on specific access requests, using head and foot switches with high voltage threshold transistors to reduce leakage current and power consumption without affecting performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If all wordline drivers are powered continuously, then memory access performance is maintained, but power consumption and leakage energy increase significantly
Solution Approach 1:
The patent segments the wordline drivers into individually controllable units, allowing selective powering of only the active wordline driver while keeping others in power-down mode. This segmentation enables fine-grained power management that reduces leakage energy without compromising the performance of the actively accessed memory location.
Solution Approach 2:
The patent implements dynamic power control for wordline drivers by introducing control logic that adjusts the power state of each driver based on real-time access patterns. The system transitions from a static all-powerful state to a dynamic selective-powering state, optimizing the balance between power consumption and access performance.
2Use of energy by moving object
If power is selectively applied to individual wordline drivers, then power consumption is reduced, but circuit complexity increases
Solution Approach 1:
The patent merges the power control function with the existing wordline driver circuitry by integrating control logic that shares resources with the driver itself. This merging approach reduces overall device complexity compared to implementing separate independent power control systems, while still achieving selective powering of wordline drivers.
Solution Approach 2:
The control logic circuit is designed to perform multiple functions: it determines which wordline driver should be activated based on address decoding, controls the power state of the selected driver, and manages the timing of power application. This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in device complexity.
3Loss of energy
If existing power-saving modes are used, then power consumption is reduced, but device complexity and overhead increase
Solution Approach 1:
The patent extracts the power control function from the processor's software-based power management modes and implements it directly within the memory device's hardware circuitry. This extraction eliminates the need for complex software-controlled power-saving modes while achieving similar or better power reduction effectiveness, thereby reducing overall device complexity.
Solution Approach 2:
The patent introduces an intermediary control logic circuit between the address decoding logic and the wordline drivers that specifically manages power application. This intermediary layer simplifies the overall system by providing a dedicated power management function that bridges the gap between control signals and power delivery, avoiding the complexity of processor-level power modes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overall power consumption by approximately 20 times in both active and non-active operational modes, conserving power for other processes and extending battery life without increasing performance overhead.
Implementation Method 1
The head switch may include a p-channel transistor and the foot switch may include an n-channel transistor
Implementation Method 2
The wordline driver is selectively powered by selectively enabling a p-channel transistor of an inverter of the wordline driver to charge a local capacitance using a diffusion capacitance associated with the plurality of wordline drivers
Implementation Method 3
charge a local capacitance using a diffusion capacitance associated with the plurality of wordline drivers
Data Source
AI summary
A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of wordline drivers. The request is decoded by a decoder to determine an address associated with the request. A wordline driver of the plurality of wordline drivers is selectively powered to access the address of the memory device, where the wordline driver is associated with a particular wordline of the plurality of wordlines that is related to the address bits, without powering other wordlines of the plurality of wordlines.