Non-volatile Memory Programming via Dynamic Bitline Bias
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Solution Overview
Problem
Current programming methods for non-volatile memory devices, such as flash memory, face issues with instant threshold voltage shift and read noise or random telegraph noise, leading to cells being programmed below target verify levels and a wide threshold voltage distribution, compromising reliability and programming speed.
Innovation Solution
The method involves applying multiple bitline bias voltages during programming loops, using a combination of low, intermediate, and system voltages based on threshold voltage comparisons with verify levels, to adjust the programming pulse and bitline bias dynamically, ensuring that cells are programmed efficiently and accurately without overshooting the target levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If incremental step pulse programming is used to achieve fast programming, then programming speed is improved, but instant threshold voltage shift causes cells to fall below target verify level
Solution Approach 1:
The patent applies dynamic bitline bias voltage adjustment during programming loops. The bitline bias voltage is changed from an initial voltage to a second voltage based on whether the cell threshold voltage passes the verify level, creating a dynamic control mechanism that adapts to the programming state and prevents threshold voltage shift issues
Solution Approach 2:
The patent implements a feedback mechanism where the verify operation result (whether threshold voltage passes verify level) controls the subsequent bitline bias voltage application. This closed-loop control allows the system to adjust programming parameters based on actual cell state, resolving the contradiction between speed and reliability
2Reliability
If multiple verify operations are applied to reduce noise-related issues, then reliability is improved, but programming speed is compromised
Solution Approach 1:
The patent uses dynamic bitline bias voltage adjustment to achieve reliable programming in fewer loops. By adapting the bias voltage based on verify results, the system reduces the number of programming loops needed compared to static multi-verify approaches, thus maintaining speed while improving reliability
Solution Approach 2:
The patent changes the bitline bias voltage parameter during programming based on cell response. This parameter adaptation allows the system to achieve better noise resistance without requiring multiple verify operations, as the dynamic parameter adjustment prevents cells from falling below verify levels in the first place
3Reliability
If higher program voltage is applied to program hard cells, then programming completeness is improved, but threshold voltage distribution becomes wider
Solution Approach 1:
The patent applies dynamic bitline bias voltage adjustment during programming loops. The bitline bias voltage is changed from an initial voltage to a second voltage based on whether the cell threshold voltage passes the verify level, creating a dynamic control mechanism that adapts to the programming state and prevents threshold voltage shift issues
Solution Approach 2:
The patent applies different bitline bias voltages to different cells based on their individual programming status. Cells that have passed the verify level receive different treatment than those that haven't, allowing precise control over each cell's threshold voltage and preventing over-programming that would widen the distribution
Data Source
AI summary
Programming in a non-volatile memory device includes applying at least one programming pulse to a non-volatile memory cell during a first programming loop; applying at least one programming pulse to the non-volatile memory cell during a second programming loop succeeding the first programming loop; and providing a bitline bias voltage of the non-volatile memory cell according to a result of comparing a threshold voltage of the non-volatile memory cell in the first programming loop with a low verify level and/or a high verify level of a target data state of the non-volatile memory cell and a result of comparing a threshold voltage of the non-volatile memory cell in the second programming loop with the low verify level and/or the high verify level of the target data state of the non-volatile memory cell.