Reversible Polarity Word Line and Bit Line Decoders for 3D Memory Arrays
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Solution Overview
Problem
In three-dimensional memory technology, the high voltages required for programming and erasing passive element memory cells pose a challenge as they do not scale well with decreasing memory cell pitch, leading to increased complexity and power dissipation in decoder and driver circuits.
Innovation Solution
The use of a circuit and method that splits the reverse bias voltage, allowing the bit line decoder and word line decoder to operate at reduced voltages, thereby relaxing the voltage requirements and reducing leakage current in unselected memory cells, enabling smaller array line pitches without significant power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used in word line and bit line decoders to handle programming and erasing voltages, then the memory cells can be programmed and erased, but the decoder circuits do not scale well as memory cell pitch decreases
Solution Approach 1:
The high voltage requirement is segmented between word line decoder and bit line decoder. The word line decoder handles the forward bias voltage (6-8V) while the bit line decoder handles the reverse bias voltage (10-14V). This segmentation allows each decoder to be optimized for its specific voltage range, improving scalability as memory cell pitch decreases.
Solution Approach 2:
The patent inverts the conventional approach by having the bit line decoder handle the higher reverse bias voltage instead of the word line decoder. This inversion allows the bit line decoder to be designed with specific transistor configurations that scale better with decreasing pitch, while the word line decoder operates at the lower forward bias voltage.
2Reliability
If high voltage transistors are used in decoder circuits, then programming and erasing can be achieved, but power dissipation increases
Solution Approach 1:
Different regions of the decoder circuit are assigned different voltage handling responsibilities. The word line decoder transistors are optimized for 6-8V operation while bit line decoder transistors are optimized for 10-14V operation. This local quality assignment reduces the overall power dissipation by ensuring each transistor operates at the minimum necessary voltage for its function.
Solution Approach 2:
The patent changes the voltage parameter distribution across the decoder circuit. Instead of all transistors handling the full 10-14V range, the voltage parameter is split so that word line decoder transistors handle 6-8V and bit line decoder transistors handle 10-14V. This parameter change reduces the average voltage stress on decoder transistors, thereby reducing power dissipation.
3Quantity of substance
If memory cell pitch is decreased to increase density, then array density improves, but the ability to provide decoder circuits compatible with smaller pitches while impressing sufficient voltage becomes more difficult
Solution Approach 1:
The voltage handling function is segmented between word line and bit line decoders, allowing each to be independently optimized for small pitch scaling. The word line decoder uses transistors sized for 6-8V operation while the bit line decoder uses transistors sized for 10-14V operation, enabling both to scale effectively with decreasing memory cell pitch.
Solution Approach 2:
The decoder circuit design is made dynamic by allowing different transistor sizes and voltage handling capabilities in different parts of the circuit. This dynamic design enables the decoders to adapt to smaller pitches while still providing the necessary voltage ranges for programming and erasing operations.
Data Source
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AI summary
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.