Nonvolatile Memory Negative Level Shifting
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently providing a negative voltage to word lines and wells, which affects the integrity and performance of memory core regions, particularly due to the location of negative level shift operations within the memory core region.
Innovation Solution
The proposed solution involves configuring a nonvolatile memory device with a pre-decoder in a peripheral region that performs negative level shifting, rather than at the row decoder within the memory core, allowing for improved integrity by securing the memory core region and optimizing voltage supply through address buffers, multiplexers, and negative level shifters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative level shifting operations are performed at the row decoder within the memory core region, then voltage supply to word lines can be achieved, but the integrity and performance of the memory core region is compromised
Solution Approach 1:
The negative level shifting operation is extracted from the row decoder within the memory core region and relocated to a peripheral region. This separation removes the harmful operation from the sensitive memory core area, preserving its integrity while maintaining the voltage supply function through dedicated negative level shifters in the periphery.
Solution Approach 2:
The device is segmented into distinct functional regions: the memory core region dedicated to high-performance memory operations and a peripheral region housing support circuits including negative level shifters. This spatial segmentation allows the core region to operate without interference from voltage conversion operations.
2Reliability
If negative level shifters are placed in the peripheral region, then the memory core region integrity is improved, but additional circuit components are required
Solution Approach 1:
Multiple negative level shifters are merged into a single peripheral region, sharing common infrastructure and control logic. This consolidation reduces the overall device complexity compared to having distributed level shifters throughout the core region, while still providing the necessary voltage conversion capability.
Solution Approach 2:
The peripheral region is designed as a multi-functional area that houses not only negative level shifters but also other support circuits. This universal peripheral structure efficiently accommodates multiple functions without proportionally increasing device complexity, as shared resources and infrastructure are utilized.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integrity of the nonvolatile memory device by ensuring the memory core region is not compromised by negative level shifting operations, leading to improved performance and reliability in voltage supply and memory operations.
Implementation Method 1
Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage.
Data Source
AI summary
A nonvolatile memory device including memory blocks, a pre-decoder, and a row decoder is disclosed. Each of the memory blocks has a plurality of memory cells. The pre-decoder includes a multiplexer and negative level shifters. The multiplexer is configured to generate multiplexing signals in response to address signals. Each of the negative level shifters is configured to generate a converted multiplexing signal corresponding to a respective multiplexing signal by converting a multiplexing signal having a ground voltage into a converted multiplexing signal having a first negative voltage. The row decoder is configured to select at least one of the memory blocks in response to the converted multiplexing signals.