Erase Suspend Bias Arrangement for Nonvolatile Memory Leakage Control
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Solution Overview
Problem
Current memory integrated circuit erase operations are time-consuming due to multiple phases, and the erase suspend command leads to current leakage from over-erased memory cells, affecting subsequent read or program operations in shared sectors.
Innovation Solution
The control logic in the integrated circuit performs a multi-phase erase procedure and applies a bias arrangement, specifically a negative voltage on word lines during the erase suspend procedure, to reduce leakage from over-erased memory cells, allowing non-erase commands like read or program operations to proceed without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an erase suspend command is received during an erase operation, then control is taken over by a new command in 20 μs, but current leakage occurs from over-erased memory cells affecting subsequent operations
Solution Approach 1:
The patent applies a preliminary counter-action by establishing a large positive voltage on the gate relative to source before the harmful current leakage can affect subsequent operations. This positive voltage counteracts the leakage current from over-erased cells, preventing it from interfering with the new command execution during the 20 μs window and beyond.
Solution Approach 2:
The patent changes the voltage parameters dynamically during the erase suspend operation. By adjusting the gate voltage to a large positive value relative to source during the suspend period, the system modifies the electrical parameters to suppress leakage current while maintaining the ability to execute new commands quickly.
2Reliability
If a multi-phase erase procedure is performed to repair over-erased memory cells, then memory cell reliability is improved, but the erase operation becomes time-consuming
Solution Approach 1:
The patent performs preliminary actions by conducting the multi-phase erase procedure including pre-programming, erase, and soft programming phases before the final verify stage. This preliminary comprehensive treatment ensures that over-erased cells are repaired in advance, improving reliability while allowing the operation to be suspended and resumed efficiently later.
Solution Approach 2:
The patent introduces dynamics to the erase operation by enabling suspend and resume capabilities. The erase operation can be paused at any phase and resumed later, making the duration flexible rather than fixed. This allows the system to balance thoroughness of the multi-phase procedure with operational efficiency by interrupting and resuming as needed.
3Adaptability or versatility
If the erase suspend operation is performed during the erase phase or soft program phase, then operational flexibility is improved, but current leakage from over-erased cells affects subsequent read or program commands
Solution Approach 1:
The patent applies preliminary anti-action by establishing a large positive voltage on the gate relative to source immediately when the erase suspend command is received, during the erase phase or soft program phase. This counteracts the current leakage from over-erased cells before it can affect subsequent read or program commands, enabling operational flexibility without the harmful leakage effect.
4Manufacturing precision
If a small sector of approximately 4 kB is used as the erase unit, then precision is improved, but current leakage affects larger shared regions of approximately 64 kB or 128 kB
Solution Approach 1:
The patent applies local quality by targeting the voltage correction specifically to the 4 kB erase sector where over-erased cells exist, while the larger 64 kB or 128 kB regions share the same well or bit line. By applying a large positive voltage specifically to the gate of cells in the affected erase sector, the leakage is suppressed locally without requiring intervention across the entire larger region, maintaining precision while limiting the spread of harmful effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bias arrangement effectively suppresses current leakage from over-erased memory cells, ensuring accurate read and program operations by isolating the impact of over-erased cells, thus reducing the duration of erase procedures and improving operational efficiency.
Implementation Method 1
The bias arrangement applies a negative voltage to at least one of the plurality of word lines accessing the erase sector during the non-erase procedure
Data Source
AI summary
Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.