Flash Memory Connectivity Testing via Boundary Scan
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Solution Overview
Problem
Current IC testing methods for flash memory chips are inefficient due to increased complexity and circuit density, leading to time-consuming and cost-ineffective connectivity tests that often sacrifice coverage or result in difficult-to-analyze data.
Innovation Solution
The implementation of specialized circuitry and boundary scan cells connected to bond pads allows for rapid connectivity testing by transmitting test signals to address, data, and control pins, using patterns like the 'walking 1' pattern to detect opens and shorts, and comparing retrieved data to identify connectivity issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive connectivity testing of every bond wire is performed, then testing coverage is improved, but testing time and cost increase significantly
Solution Approach 1:
The testing approach segments the bond wire connectivity testing into two distinct phases: (1) wafer-level boundary scan testing that provides rapid initial screening using embedded scan cells, and (2) post-bonding targeted re-testing that focuses only on potentially problematic areas. This segmentation allows comprehensive coverage to be achieved without requiring exhaustive testing of every bond wire at the same level of detail, thereby reducing overall testing time while maintaining reliability.
Solution Approach 2:
The patent implements preliminary connectivity testing at the wafer level using boundary scan cells before the actual wire bonding process occurs. This preliminary action establishes a baseline of expected connectivity patterns and identifies potential issues early in the manufacturing process, allowing for corrective measures to be taken before time-consuming post-bonding testing is required, thus reducing the net testing time needed.
2Reliability
If comprehensive connectivity testing of every bond wire is performed, then testing coverage is improved, but testing cost increases significantly
Solution Approach 1:
The testing cost is segmented and optimized by performing the majority of connectivity verification at the wafer level using integrated boundary scan cells, which are more cost-effective than post-bonding probing methods. Only targeted re-testing of specific areas is performed after bonding, reducing the need for expensive comprehensive post-assembly testing while maintaining adequate coverage for critical connectivity paths.
Solution Approach 2:
The boundary scan cells are self-contained within the IC and can autonomously perform connectivity testing without requiring external testing equipment or complex test fixtures. This self-service capability reduces the need for expensive external testing infrastructure and manual intervention, thereby lowering overall testing costs while maintaining comprehensive coverage of connectivity paths.
3Productivity
If testing methods are simplified to reduce testing time, then productivity is improved, but test data becomes difficult to analyze
Solution Approach 1:
The boundary scan cells provide structured feedback mechanisms that automatically capture and report connectivity test results in a standardized format. The testing system incorporates feedback loops that compare actual connectivity measurements against expected patterns, automatically identifying deviations and generating actionable diagnostic information. This feedback structure maintains data analyzability even as testing speed increases, because the automated comparison and reporting systems process results efficiently without requiring manual analysis of raw data.
Data Source
AI summary
In one embodiment of the invention, circuitry and hardware for connectivity testing are fabricated on an IC, and in particular an IC containing a flash memory array. This testing circuitry is electrically connected to the bond pads of the IC. In some embodiments, the testing circuitry includes a boundary scan cell connected to each bond pad, allowing for rapid connectivity testing of flash memory chips in accordance with testing standards such as the JTAG standard. The invention further includes methods in which the pins and/or memory cells of a flash memory chip are sequentially sent a series of data so as to test the connectivity of portions of the IC. The sequentially-sent data is then retrieved and compared to the original data. Discrepancies between these sets of data thus highlight connectivity problems in the IC.