Memory Architecture with Independent Voltage Pumps
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Solution Overview
Problem
The scalability of floating gate non-volatile memory technology is limited by capacitive coupling and manufacturing defects, and the voltage mismatch between tunneling and circuit operating voltages leads to wear out of memory devices during write/erase cycles.
Innovation Solution
A memory architecture using SONOS technology with independently controlled voltage pumps to apply both positive and negative voltage biases to the storage node of memory cells, allowing for robust programming and erasing with reduced wear out and immunity to pinhole defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If floating gate NVM technology is scaled down to smaller dimensions, then memory density is improved, but capacitive coupling between memory bits increases and manufacturing defects create discharge paths
Solution Approach 1:
The patent uses a composite dielectric structure consisting of multiple layers (tunnel oxide, charge trapping layer, blocking oxide) instead of a simple floating gate. This composite structure isolates the charge storage function from the transistor gate, preventing capacitive coupling issues while maintaining scalability to smaller dimensions.
Solution Approach 2:
The patent extracts the charge storage function from the transistor gate by introducing a separate charge trapping layer. This separation allows the transistor to be scaled down without the gate becoming susceptible to capacitive coupling and pinhole defects, thereby maintaining reliability while improving density.
2Quantity of substance
If device dimensions are shrunk to increase density, then memory capacity is improved, but the voltage mismatch between tunneling voltage and circuit operating voltage increases
Solution Approach 1:
The patent segments the voltage control function by introducing separate control gates (first control gate and second control gate) that can independently apply voltages to different regions of the charge trapping layer. This segmentation enables precise control of tunneling voltages without affecting the overall circuit operating voltage, reducing voltage control complexity while maintaining high capacity.
3Speed
If high voltage is applied to induce tunneling for programming/erasing, then write speed is improved, but wear out of the floating gate transistor increases
Solution Approach 1:
The patent introduces a charge trapping layer as an intermediary between the tunnel oxide and the transistor channel. This intermediary layer captures charges during tunneling, preventing direct interaction between high voltage tunneling currents and the transistor channel, thereby reducing wear out while maintaining fast write speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention and reduces wear out by using charge trapping in a nitride layer, minimizing the impact of defects and voltage mismatches, thereby improving the reliability and longevity of memory cells.
Implementation Method 1
charge is injected from the channel to the floating gate through the tunnel oxide. The method of injection may be through direct Fowler-Nordheim (FN) tunneling
Implementation Method 2
using charge trapping in a nitride layer
Data Source
AI summary
A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.