Page Buffer Cross-Coupled Transistors Voltage Stability
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Solution Overview
Problem
Memory devices face challenges in reducing current consumption and maintaining operational stability due to fluctuations in internal voltage, which affects the recognition of data output from non-volatile memory cells and increases the size of the page buffer, thereby reducing integration density.
Innovation Solution
A page buffer design with cross-coupled transistors and a latch structure that is insensitive to internal voltage fluctuations, allowing for efficient data recognition from non-volatile memory cells and reducing the size of the page buffer by eliminating the need for long channel transistors, thereby enhancing integration density and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional page buffer design is used, then data recognition from non-volatile memory cells is achieved, but current consumption increases and integration density decreases due to larger page buffer size
Solution Approach 1:
The patent changes the transistor configuration parameters by using cross-coupled transistor pairs instead of conventional long channel transistors. This parameter change reduces the page buffer size and current consumption while maintaining operational stability through the latch structure's insensitivity to voltage fluctuations.
Solution Approach 2:
The patent replaces the conventional mechanical/transistor-based page buffer design with a cross-coupled transistor latch structure that uses feedback mechanisms. This substitution eliminates the need for long channel transistors and reduces the overall page buffer size, thereby increasing integration density.
2Area of stationary object
If page buffer size is reduced to increase integration density, then integration density improves, but data recognition accuracy may be affected under voltage fluctuations
Solution Approach 1:
The patent employs a feedback mechanism through cross-coupled transistor pairs that form a latch structure. This feedback mechanism maintains stable data recognition by continuously reinforcing the stored state, making the page buffer insensible to voltage fluctuations while keeping the size compact.
Solution Approach 2:
The latch structure provides beforehand cushioning against voltage fluctuations by using cross-coupled transistors that preemptively compensate for voltage variations. This ensures data recognition accuracy is maintained even when power supply voltage varies, without requiring additional buffer space.
3Reliability
If cross-coupled transistor latch structure is used, then operational stability improves and current consumption reduces, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the cross-coupled transistor latch structure. The same cross-coupled transistors serve both as the storage element and as the feedback mechanism, eliminating the need for separate components. This merging reduces the overall device complexity despite the sophisticated latch operation.
Data Source
AI summary
A memory device includes a cell string comprising a plurality of memory cells and a page buffer coupled to the cell string. The page buffer includes a latch with cross-coupled transistors. Data transferred from the cell string to the page buffer is input to gates of plural transistors included in the page buffer.