Semiconductor Device with Overlapping Memory and Arithmetic Circuits
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Solution Overview
Problem
Current semiconductor devices for healthcare systems face challenges in reducing area, achieving high-speed operation, and minimizing power consumption while effectively storing and processing biological data.
Innovation Solution
A semiconductor device is designed with a structure that includes overlapping regions of memory and arithmetic circuits, utilizing oxide semiconductors to enhance data storage and processing capabilities, allowing for efficient data acquisition, conversion, and comparison of biological data against reference values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory circuit and arithmetic circuit are arranged separately without overlapping, then circuit design is simple, but device area increases
Solution Approach 1:
The patent applies three-dimensional stacking architecture where the memory circuit is formed on a first substrate and the arithmetic circuit is formed on a second substrate positioned above the first substrate. This vertical arrangement in the third dimension enables overlapping regions between the two circuits, significantly reducing the planar area of the device while maintaining functional separation and design simplicity.
2Speed
If conventional semiconductor devices are used, then manufacturing is straightforward, but operation speed is limited
Solution Approach 1:
The patent employs oxide semiconductor transistors with specific material parameters (bandgap, carrier mobility) that enable high-speed operation. The oxide semiconductor layer is formed with controlled thickness and composition to achieve optimal electrical characteristics for fast switching and processing, thereby increasing operation speed while using established semiconductor manufacturing techniques.
3Use of energy by moving object
If conventional semiconductor devices are used, then manufacturing is straightforward, but power consumption is high
Solution Approach 1:
The patent utilizes oxide semiconductor transistors whose material properties (wide bandgap, low off-state current) inherently reduce power consumption. The oxide semiconductor layer parameters are optimized to minimize leakage current while maintaining functionality, enabling low-power operation without requiring complex manufacturing processes.
4Area of stationary object
If circuit area is reduced through integration, then device size decreases, but processing speed may slow down
Solution Approach 1:
The patent resolves the area-speed tradeoff by stacking circuits vertically in three dimensions. The memory circuit on the first substrate and arithmetic circuit on the second substrate overlap in the planar view but are separated vertically, reducing circuit area while maintaining short interconnect lengths and fast processing speeds through the vertical architecture.
Data Source
AI summary
Provided is a semiconductor device capable of reducing its area, operating at a high speed, or reducing its power consumption. A circuit 50 is used as a memory circuit with a function of performing an arithmetic operation. One of a circuit 80 and a circuit 90 has a region overlapping with at least part of the other of the circuit 80 and the circuit 90. Accordingly, the circuit 50 can perform the arithmetic operation that is essentially performed in the circuit 60; thus, a burden of the arithmetic operation on the circuit 60 can be reduced. Moreover, the number of times of data transmission and reception between the circuits 50 and 60 can be reduced. Furthermore, the circuit 50 functioning as a memory circuit can have a function of performing an arithmetic operation while the increase in the area of the circuit 50 is suppressed.