Integrated Circuit Redundancy Repair via Fuse Position Encoding

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Solution Overview

Problem

Conventional defect repair methods for memory circuits with redundancy require storing and managing defect information under multiple conditions, leading to increased test time, power consumption, and costs due to the need for external storage and prolonged tester occupation.

Innovation Solution

An integrated circuit with a redundancy control circuit that stores repair information as bit position information of cut fuses, allowing for comparison with new test results without external storage, reducing the need for prolonged testing and power supply.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If defect information is stored externally under multiple test conditions, then complete defect coverage is achieved, but test time and tester occupation increase significantly

Engineering Contradiction:
Improvedefect coverageVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The fuse array is designed to serve multiple functions: it stores repair information from different test conditions while also enabling defect repair. By making the fuse array universal for both storage and repair operations, the patent eliminates the need for separate external storage, thereby reducing test time while maintaining complete defect coverage across multiple conditions

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent extracts the storage function from external devices and relocates it directly into the fuse array within the integrated circuit. This extraction of the storage function from the external testing environment allows defect information to be retained without occupying tester resources, thus reducing test time and improving efficiency

Inventive Principle:
Principle #2Taking out (Extraction)

2Loss of information

If defect information is held in registers during condition changes, then information is preserved, but power consumption increases due to continuous power supply requirement

Engineering Contradiction:
Improvedefect information retentionVSAvoidpower consumption
Core Design Contradiction:
Loss of informationVSUse of energy by moving object

Solution Approach 1:

The patent employs fuses that can be programmed once and then remain in a stable, non-volatile state. Unlike registers that require continuous power to maintain data, the fuse-based storage uses a disposable programming approach where the repair information is written once and permanently retained without requiring ongoing power supply, thus eliminating the power consumption issue while preserving defect information

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Device complexity

If external storage is used for repair information, then data management is simplified, but device complexity and cost increase

Engineering Contradiction:
Improvestorage managementVSAvoidmanufacturing cost
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The patent merges the storage function with the existing fuse array structure used for repair operations. By combining defect information storage with the repair mechanism into a single integrated system, the patent avoids adding separate external storage components, thereby reducing device complexity and manufacturing cost while maintaining efficient data management

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS8238177B2Integrated circuit
Publication Date: 2012.08.07 RENESAS ELECTRONICS CORP
  • US8238177B2 patent drawing
  • US8238177B2 patent drawing
  • US8238177B2 patent drawing

AI summary

Provided is an integrated circuit including: multiple memory cells; a redundant memory having a function of repairing a defective cell included in the multiple memory cells by placing a corresponding fuse among multiple fuses into a first state; a fuse data conversion circuit that generates first information of a first defective cell based on position information of the fuse placed into the first state corresponding to the first defective cell having been repaired; a repair data generation circuit that generates, upon detection of a second defective cell as a result of a test for the multiple memory cells, repair information for repairing the second defective cell according to the first information and second information of the second defective cell; and a fuse state change circuit that places a predetermined fuse among the multiple fuses into the first state according to the repair information generated by the repair data generation circuit.