eFuse Memory Array Program Bit Line Resistivity Reduction
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Solution Overview
Problem
Existing electrical fuse (eFuse) memory arrays face challenges in optimizing the design of program and read transistors to efficiently manage programming and reading operations, leading to inefficiencies in current delivery and resistivity, particularly with low-resistivity eFuses requiring higher program currents.
Innovation Solution
The eFuse memory array is reconfigured by arranging multiple bit cells to share program bit lines, reducing the length and increasing the width of these lines, which lowers resistivity and allows for higher program currents without increasing the array's total area, using a combination of transistor sizing and interconnect structures to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the program bit line length is increased to connect more bit cells, then the array area can be expanded, but the resistivity of the program bit line increases, reducing current delivery efficiency
Solution Approach 1:
The patent divides the array into multiple blocks, each with its own program bit line originating from a common pad. This segmentation allows each program bit line to remain short while still accessing multiple bit cells through the block structure, thereby maintaining low resistivity and high current delivery efficiency while expanding the total array area.
2Productivity
If the program current is increased to program low-resistivity eFuses, then the programming speed improves, but the transistor sizing becomes more complex and power consumption increases
Solution Approach 1:
The patent implements different transistor sizing strategies for different locations in the array. Program transistors in blocks closer to the pad are sized differently from those farther away, optimizing the current delivery for each location. This local quality approach allows high programming speeds for low-resistivity eFuses while managing transistor sizing complexity through systematic variation rather than uniform design.
3Reliability
If the program bit line width is increased to reduce resistivity, then the current delivery improves, but the array area increases
Solution Approach 1:
The patent uses a two-dimensional block structure where multiple bit cells are organized in rows and columns within each block. Program bit lines extend horizontally across blocks while word lines extend vertically, creating a grid structure. This dimensional organization allows short program bit line segments to access multiple bit cells through the block matrix structure, achieving low resistivity without increasing array area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the resistivity of program bit lines to a quarter of the original value, enabling increased program currents while maintaining or reducing the array's area, thereby enhancing the efficiency and performance of eFuse memory operations.
Implementation Method 1
Applying a program current to the eFuse destroys (i.e. fuses) the link, thus changing the resistivity of the eFuse
Implementation Method 2
The fuse state (i.e., whether it has been programmed) can be read using a sense circuit common in the art of electronic memories
Data Source
AI summary
A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resistivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.