Memory Controller Read Voltage Optimization for Latency Reduction
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Solution Overview
Problem
Memory systems face inefficiencies in read operations due to high error bit rates, leading to repeated retry processes that increase latency and power consumption.
Innovation Solution
A memory system with a controller that performs multiple read operations using different voltage strategies, including a read history table and an e-boost operation to detect optimal read voltages, thereby skipping unnecessary retry operations when error bits exceed a threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read retry operations are performed to correct error bits, then data reliability is improved, but read latency increases
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting read voltage levels based on the number of error bits detected. When error bits exceed a threshold, the system changes the read voltage parameter to optimize data retrieval, avoiding unnecessary retry operations and reducing read latency while maintaining data reliability.
Solution Approach 2:
The patent segments the read operation into multiple processing paths based on error bit thresholds. The read processor is divided into first, second, third, and fourth read processors that handle different error scenarios separately, allowing the system to skip unnecessary retry operations and reduce overall read latency.
2Reliability
If multiple read retry operations are performed to correct error bits, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent changes the read voltage parameter dynamically based on error bit counts. By adjusting the voltage parameter rather than performing multiple full retry operations, the system reduces power consumption while still achieving the necessary data reliability through targeted voltage adjustments.
Solution Approach 2:
The patent segments power consumption across different read processor paths. By directing error correction through specific processors (second, third, or fourth read processors) based on error thresholds, the system optimizes power usage by avoiding unnecessary activation of all retry mechanisms simultaneously.
3Productivity
If e-boost operation is performed to detect optimal read voltage, then read operation efficiency is improved, but device complexity increases
Solution Approach 1:
The patent performs preliminary action by implementing an e-boost operation that detects optimal read voltage in advance. This preliminary voltage optimization is executed before main read operations, allowing the system to improve read efficiency without adding complexity during critical data retrieval paths.
Solution Approach 2:
The patent introduces an intermediary e-boost operation that acts as a mediator between the controller and main read processors. This intermediary component handles the complex voltage detection task separately, allowing the core read processors to remain relatively simple while still benefiting from optimized voltage settings.
Data Source
AI summary
A memory system includes a memory device, and a controller suitable for correcting errors included in request data read through a first read operation performed by the memory device in response to a read command provided from a host, and providing corrected data to the host, wherein the controller includes a first read processor suitable for performing the first read operation, a second read processor suitable for performing a second read operation, a third read processor suitable for performing a third read operation, and a fourth read processor suitable for detecting an optimal read voltage through an e-boost operation and performing a fourth read operation.