Two-Side Staircase Pre-Charge for Non-Volatile Memory Disturb Reduction
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Solution Overview
Problem
As memory structures increase in density, maintaining data integrity becomes challenging due to issues like charge leakage and 'disturb' effects during read/write operations in non-volatile memory cells, leading to data degradation over time.
Innovation Solution
A memory apparatus and method where voltages are ramped from a verify voltage to a reduced voltage during program-verify operations, with neighboring word lines progressively adjusting from a read pass voltage, addressing the data integrity issues by managing stress across memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory structures increase in density to improve storage capacity, then storage capacity is improved, but data integrity deteriorates due to charge leakage and disturb effects
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting voltage levels during program-verify operations. Specifically, the verify voltage is ramped down from an initial higher level to a reduced level as programming progresses, and neighboring word line voltages are progressively reduced to minimize disturb effects. This dynamic parameter adjustment resolves the contradiction by maintaining reliable data integrity while enabling high-density storage operations.
2Measurement precision
If verify voltage is maintained at high level during program operation to ensure accurate verification, then verification accuracy is improved, but stress on memory cells increases causing data degradation
Solution Approach 1:
The patent implements dynamics by making the verify voltage time-dependent rather than static. The verify voltage starts at a higher level for initial verification accuracy, then is progressively reduced during subsequent program-verify cycles. This dynamic voltage adjustment maintains verification precision when needed while reducing stress-induced data degradation over time, resolving the contradiction between measurement precision and harmful stress effects.
Solution Approach 2:
The patent applies periodic action through multiple program-verify cycles with progressively adjusted voltage levels. Each cycle performs verification at the current voltage state, then reduces the voltage for the next cycle. This periodic verification with decreasing amplitude ensures accurate measurement early in the process while minimizing cumulative stress damage, effectively resolving the contradiction between verification accuracy and stress reduction.
3Productivity
If voltages are applied to all word lines simultaneously during programming, then programming speed is improved, but disturb effects on neighboring cells increase
Solution Approach 1:
The patent applies preliminary action by pre-charging neighboring word lines to appropriate voltage levels before initiating programming on the selected word line. This preliminary voltage setup ensures that when programming occurs, neighboring cells are already in a state that minimizes disturb effects. This approach maintains programming speed while preventing harmful disturb effects through advance preparation of the electrical environment.
Solution Approach 2:
The patent implements local quality by applying different voltage levels to different word lines based on their spatial relationship to the selected word line. Neighboring word lines receive progressively reduced voltages compared to the selected word line, creating a localized voltage gradient that confines programming effects to the intended cells. This spatially differentiated voltage application maintains overall programming efficiency while eliminating harmful disturb effects on specific neighboring cells.
Data Source
AI summary
A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.