Vertical Memory Cell String Asymmetric Spacer Design
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Solution Overview
Problem
Current vertical nonvolatile memory devices face challenges in reducing the thickness of memory cell strings while maintaining the density and accessibility of memory cells, particularly in achieving high density and low power consumption for next-generation neuromorphic computing platforms.
Innovation Solution
The proposed solution involves reducing the thickness of individual memory cells within a memory cell string by optimizing the dimensions and arrangements of insulating spacers and gate electrodes, which are alternately stacked and feature inclined peripheral side surfaces. This configuration allows for a reduction in the overall thickness of the memory cell string while increasing the number of stacked memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If the thickness of individual memory cells is reduced, then the entire thickness of the memory cell string is reduced and the number of stacked memory cells is increased, but the manufacturing precision and structural stability become more difficult to maintain
Solution Approach 1:
The gate electrodes and insulating spacers are configured with asymmetric dimensions where the width of insulating spacers gradually decreases in the second direction, and the peripheral side surfaces are inclined rather than vertical. This asymmetric design allows for optimized electrical characteristics and improved manufacturing tolerances while maintaining reduced cell thickness
Solution Approach 2:
Different regions of the gate electrodes and insulating spacers have different dimensions and orientations. The inclined peripheral side surfaces create local variations in width that optimize both the electrical performance and mechanical stability of the structure, allowing precise control at critical interfaces while maintaining overall compactness
2Quantity of substance
If the number of stacked memory cells is increased, then the memory density is enhanced, but the device complexity and difficulty of detecting and measuring individual cells increase
Solution Approach 1:
The memory cell string is segmented into repeating units of gate electrodes and insulating spacers arranged in a regular alternating pattern. This segmentation into standardized modules simplifies the overall structure despite the high number of cells, making fabrication and characterization more manageable through repetition of proven design units
Solution Approach 2:
The memory cells are arranged in a vertical stack along the first direction, transitioning from a planar two-dimensional layout to a three-dimensional vertical architecture. This dimensional change allows significantly higher cell density without increasing the planar footprint, and the regular alternating pattern of components along the vertical axis maintains structural regularity that simplifies complexity management
Data Source
AI summary
Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.