Nonvolatile Memory Verify Read Error Detection
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Solution Overview
Problem
Nonvolatile semiconductor memories face issues with subtle increases in word line resistance, which can allow program operations to complete successfully but result in read errors, leading to system failures and permanent data loss, as existing technologies fail to detect these errors before program termination.
Innovation Solution
The proposed solution involves a nonvolatile semiconductor memory system that includes a verify circuit to judge program completion, a read operation to detect read errors after program verification, and a data latch circuit that continues to store program data even after verification, allowing for status information to be output to an external controller, enabling detection of read errors and potential re-execution of the program.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a program verify operation is performed to judge program completion, then program completion can be detected, but subtle read errors caused by word line resistance increases cannot be detected, leading to false positive program completion status
Solution Approach 1:
The patent performs a read operation immediately after the program verify operation to detect read errors before the external controller assumes successful program completion. This preliminary detection action prevents false positive completion status from causing data loss, as the read operation can identify subtle word line resistance issues before the controller finalizes the program status.
2Productivity
If the external controller assumes program completion based on verify operation alone, then processing efficiency is improved, but data integrity is compromised due to undetected read errors
Solution Approach 1:
The patent introduces a feedback mechanism where the memory device performs an additional read operation after program verification and communicates the result to the external controller. This feedback loop allows the controller to receive accurate status information about both program completion and read accuracy, enabling informed decisions about whether to proceed with data usage or retry the program operation.
3Device complexity
If no additional read operation is performed after program verification, then device complexity is reduced, but system errors occur due to undetected word line resistance issues
Solution Approach 1:
The patent implements self-service by having the memory device automatically perform the additional read operation and determine the final program status without requiring explicit instructions from the external controller. The memory device monitors its own operational health during and after program verification, detecting read errors and controlling the final status communication to the controller, thereby preventing system errors while maintaining simplicity.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory includes a control circuit. The control circuit is configured to repeat an application of a write pulse and a verify read operation to a selected word line, perform a read operation from a selected memory cell after storing of program data is judged to be completed by a verify circuit, and output a status information indicating that a program operation has passed to a external controller when data read by a read operation and a program data match and the status information indicating that the program operation has failed to the external controller when both do not match. A data latch circuit continues to latch the program data even after the storing of the program data is judged to be completed by the verify circuit.