Dynamic Redundancy Repair for Phase Change Memory
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Solution Overview
Problem
Error Correction Code (ECC) techniques are inadequate for phase change memories, especially when the resistance level of the status bit drifts, making it challenging to read data accurately without additional correction mechanisms.
Innovation Solution
A memory device with dynamic redundancy repair technology that includes a memory array, a redundancy array, and a redundancy mapping store, where circuitry writes data to redundancy cells if the primary cell fails verification during write operations and maps the address to the redundancy cell, allowing for read operations from either the memory or redundancy array based on valid entries in the mapping store.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC techniques are used to detect and correct errors in phase change memories, then data reliability is improved, but system complexity increases and ECC cannot reliably correct errors when status bit resistance drifts occur
Solution Approach 1:
The patent applies preliminary action by performing write verification immediately after writing data to phase change memory cells. The verify circuit checks whether the written data is correctly stored by reading back and comparing with expected values. If verification fails, the system automatically retries the write operation or activates redundancy mechanisms before the error affects subsequent read operations. This proactive verification approach prevents error propagation without requiring complex ECC decoding circuits.
Solution Approach 2:
The patent implements copying by maintaining redundant copies of critical data in alternative memory locations. When a phase change memory cell fails verification or exhibits resistance drift, the system copies the valid data to a backup location or uses a previously verified copy. This copying mechanism provides fault tolerance without needing complex error correction algorithms, as the system can simply switch to using the copied valid data.
2Measurement precision
If write verification is performed on every write operation to detect defective cells, then data accuracy is improved, but write operation time increases
Solution Approach 1:
The patent applies partial action by performing verification selectively rather than on every single write operation. The verify circuit is activated based on conditions such as detected resistance drift, previous error patterns, or critical data writes. For routine writes to stable memory cells, verification may be reduced or omitted. This selective verification approach maintains data accuracy for critical operations while minimizing the time overhead for常规 writes.
Solution Approach 2:
The patent implements continuity of useful action by overlapping verification activities with subsequent operations. While verification is performing on recently written data, the system can simultaneously prepare for or initiate the next write operation. The verify circuit operates continuously in the background, and verification results are integrated into the normal write workflow without requiring complete operation停顿. This allows the system to maintain high verification coverage while keeping the average write time penalty minimal.
Data Source
AI summary
The disclosed memory device technology for implementing dynamic device repair includes a memory array, a redundancy array and a redundancy mapping store. The memory array includes memory cells and the redundant array includes redundancy cells. The memory device also includes circuitry configured to execute a write operation and a read operation in response to respective commands, using a dynamic redundancy repair method to replace the temporary defective cells in the memory array with the redundancy cells in the redundancy array.