3D NAND Contact Structure With Spacer-Defined Peripheral Contacts
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Solution Overview
Problem
The fabrication of planar memory cells faces challenges as they approach a lower size limit, leading to increased complexity and cost, while 3D memory architectures face difficulties in forming peripheral contacts due to lengthy and complex etching and deposition processes.
Innovation Solution
The formation of contact structures in 3D NAND memory devices involves creating a spacer structure on the front side of the base structure through etching and deposition processes, simplifying the fabrication by integrating these steps into the existing process flow without additional steps, and forming the second contact portion within the spacer structure to ensure a flat upper surface coplanar with the conductive layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but fabrication complexity and cost increase
Solution Approach 1:
The patent transitions from planar 2D memory cell architecture to 3D vertical memory architecture. Memory cells are stacked vertically with multiple levels, allowing density improvement without proportionally increasing fabrication complexity. The vertical stacking enables higher memory density by utilizing the third dimension while maintaining compatible manufacturing processes.
2Quantity of substance
If 3D memory architecture is implemented to address density limitation, then memory density is improved, but peripheral contact formation becomes lengthy and complex
Solution Approach 1:
The spacer structure is formed in advance during the memory stack fabrication process, before peripheral contacts need to be created. This preliminary formation of spacers with appropriate openings eliminates the need for separate, lengthy etching and deposition steps later, significantly reducing contact formation time while maintaining the 3D architecture's density advantages.
Solution Approach 2:
The patent combines the spacer formation process with the existing memory stack fabrication process. The same etching and deposition steps used to create the memory structure also form the spacers that will later accommodate peripheral contacts, merging multiple functions into a single integrated process flow.
3Reliability
If traditional etching and deposition processes are used for peripheral contacts in 3D memory, then contact formation is achieved, but process complexity increases
Solution Approach 1:
Spacers are formed preliminarily during memory stack fabrication with pre-defined openings positioned for peripheral contacts. This eliminates the need for separate complex etching and deposition steps, reducing process complexity while ensuring reliable contact formation through the pre-prepared pathways.
Solution Approach 2:
The spacer structure serves multiple functions: it provides mechanical support, defines contact locations, and creates the necessary openings for peripheral contacts all during a single formation process. This multi-functionality reduces the number of specialized steps needed, lowering overall process complexity.
Data Source
AI summary
Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a method for forming a semiconductor device includes forming a spacer structure from a first surface of the base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact extends from a second surface of the base structure into the base structure.