3D NAND Staircase Bridge Layout for Lower Word Line Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As 3D NAND memory devices increase in storage capacity, the distance between memory cells and electrical connections leads to larger parasitic resistance and slower read/write speeds, necessitating improvements in staircase structures to maintain performance while enhancing storage density.
Innovation Solution
The introduction of a staircase region with two symmetric staircase structures and a connecting staircase bridge in the 3D memory device, which reduces routing congestion and manufacturing costs by allowing for more efficient electrical connections and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells and memory array size are increased to increase storage capacity, then storage density is improved, but the distance between memory cells and electrical connections increases leading to larger parasitic resistance and slower read/write speed
Solution Approach 1:
The patent divides the memory array into multiple segments with separate staircase structures for different regions (e.g., first staircase structure for first region, second staircase structure for second region). This segmentation reduces the distance between memory cells and electrical connections in each segment, thereby reducing parasitic resistance while maintaining high storage capacity through the combined array.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional vertically stacked memory cells. By stacking memory cells vertically, the patent increases storage density without proportionally increasing the lateral distance to electrical connections, thus improving storage capacity while controlling parasitic resistance.
2Quantity of substance
If the number of memory cells and memory array size are increased to increase storage capacity, then storage density is improved, but read/write speed deteriorates due to larger parasitic resistance
Solution Approach 1:
The patent divides the memory array into multiple segments with separate staircase structures for different regions (e.g., first staircase structure for first region, second staircase structure for second region). This segmentation reduces the distance between memory cells and electrical connections in each segment, thereby reducing parasitic resistance while maintaining high storage capacity through the combined array.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional vertically stacked memory cells. By stacking memory cells vertically, the patent increases storage density without proportionally increasing the lateral distance to electrical connections, thus improving storage capacity while controlling parasitic resistance.
3Ease of manufacture
If traditional single staircase structure is used, then manufacturing is simpler, but routing congestion increases and area usage is less efficient
Solution Approach 1:
The patent divides the memory array into multiple segments with separate staircase structures for different regions (e.g., first staircase structure for first region, second staircase structure for second region). This segmentation reduces the distance between memory cells and electrical connections in each segment, thereby reducing parasitic resistance while maintaining high storage capacity through the combined array.
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, the 3D memory device includes a film stack having a plurality of conductive and dielectric layer pairs vertically stacked on a substrate. Each conductive and dielectric layer pair includes a dielectric layer and a conductive layer. The 3D memory device also includes a staircase region having a first and a second staircase structure formed in the film stack, where the first and second staircase structures each extends laterally in a first direction and includes the plurality of conductive and dielectric layer pairs. The staircase region further includes a staircase bridge connecting the first and second staircase structures.