3D NAND Staircase Stack Structure to Minimize Tier Deformation
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Solution Overview
Problem
Conventional methods of forming 3D NAND memory devices result in deformations such as tier shrinking, tier dishing, and tier bending, leading to undesirable defects, reduced performance, and decreased reliability and durability due to deformations in staircase regions of the tiered stack.
Innovation Solution
A method is introduced to form microelectronic devices with staircase structures by using a sequence of conductive and insulative materials in tiers, employing a controlled etching process to create slots and contact structures, and forming conductive materials to minimize deformations and enhance structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional replacement gate or gate last processing is used to form the tiered stack, then the fabrication process can be completed, but deformations such as tier shrinking, tier dishing, and tier bending occur in staircase regions
Solution Approach 1:
The patent applies preliminary action by forming a stress compensation structure (such as a dummy tier or stress layer) before completing the tiered stack fabrication. This pre-formed structure compensates for expected deformations in staircase regions, preventing tier shrinking, dishing, and bending that would otherwise occur during conventional replacement gate or gate last processing.
2Productivity
If feature packing density is increased to maximize device count, then more devices fit in a given area, but margins for formation errors decrease leading to deformations
Solution Approach 1:
The patent implements beforehand cushioning by introducing stress compensation structures that act as buffers against formation errors. These structures absorb or counteract the effects of packing density increases, maintaining staircase region integrity even when features are closely spaced to maximize device count in a given area.
3Reliability
If deformations in staircase regions are reduced, then reliability and durability improve, but additional process steps or structures are required
Solution Approach 1:
The patent uses an intermediary approach by introducing stress compensation structures (dummy tiers or stress layers) that mediate between the fabrication process and the final device structure. These intermediary elements prevent deformations during manufacturing while being designed to be removed or integrated seamlessly into the final device, thus improving reliability without permanently increasing device complexity.
Data Source
AI summary
A microelectronic device includes a stack structure, slot structures, and dielectric material. The stack structure includes blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks includes an array region including strings of memory cells, and a staircase region including a crest sub-region interposed between a staircase structure and the array region. An uppermost boundary of the tiers within the crest sub-region underlies an uppermost boundary of the tiers within the array region. The slot structures are interposed between the blocks of the stack structure. The dielectric material extends over and between the blocks of the stack structure. A thickness of a portion of the dielectric material overlying the crest sub-region is greater than a thickness of an additional portion of the dielectric material overlying the array region. Related memory devices, electronic systems, and methods are also described.