3D NAND ISPP Step-Voltage Control for Faster High-State Programming

The patent applies dynamics by transitioning from a fixed step pulse to a variable step pulse that changes based on programming state. The step pulse is increased when certain conditions are met (e.g., after successful programming of lower states, or after a predetermined number of pulses), allowing the system to adapt the pulse size dynamically. This resolves the contradiction by using small pulses initially for accuracy, then switching to larger pulses for speed when accuracy is already established.

The patent changes the parameter of step pulse size based on programming conditions. By monitoring programming state and adjusting the step pulse parameter accordingly, the system can optimize both accuracy and speed. The parameter change is triggered by conditions such as reaching target states or completing predetermined pulse counts, allowing the system to balance between programming accuracy and speed throughout the process.

The system dynamically adjusts the step pulse size based on the current programming state and voltage level. When programming lower states, small step pulses ensure completeness and accuracy. When transitioning to higher states or after predetermined pulses, the step pulse increases to reduce the number of remaining rounds, thereby decreasing total programming time while maintaining completeness through state-dependent verification.

The patent implements feedback mechanisms where the programming controller monitors programming state, voltage levels, and pulse counts. Based on this feedback, the controller determines when to increase step pulses or adjust programming parameters. This feedback loop ensures programming completeness is maintained while optimizing time by avoiding unnecessary additional rounds when the target state is already reached or verified.

The system dynamically adjusts step pulse size based on programming state and read-window margin requirements. When programming lower states where read-window margin is critical, small step pulses are used to maintain narrow threshold voltage distributions. When programming higher states like P7 where the read-window margin is less critical or already established, larger step pulses are applied to maximize programming speed, thus resolving the contradiction between speed and margin preservation.

The patent applies local quality by treating different programming states differently in terms of step pulse size. Each state (P1-P7) has different requirements for read-window margin and programming speed. The system optimizes the step pulse locally for each state, using smaller pulses for states requiring high precision and larger pulses for states where speed is prioritized, thereby achieving overall optimization without compromising critical read-window margins.