3D NAND Sub-Block Erase Control for Voltage Distribution
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Solution Overview
Problem
In NAND type flash memory with a three-dimensional structure, the threshold voltage of memory cells varies when data is written in one cell and subsequently in another cell within the same memory string, leading to an expansion of the threshold voltage distribution during erasing and writing operations, which affects data integrity and storage capacity.
Innovation Solution
A nonvolatile semiconductor memory device that includes a memory cell array divided into sub-blocks, with a control unit adjusting the verification level for word lines based on flag data indicating whether data has been written in adjacent sub-blocks, setting a higher verification level for non-selected sub-blocks to prevent threshold voltage distribution expansion during erasing and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written in memory cells sequentially in the same memory string, then storage capacity is improved, but threshold voltage distribution expands affecting data integrity
Solution Approach 1:
The memory string is divided into multiple sub-blocks, each with its own word line. This segmentation allows independent writing and erasing operations for each sub-block, preventing threshold voltage expansion in one sub-block from affecting others, thus maintaining data integrity while enabling sequential writing for high storage capacity.
Solution Approach 2:
Different verification levels are applied to different word lines based on whether their corresponding sub-blocks have been previously written. This local differentiation of verification levels prevents threshold voltage distribution expansion in sub-blocks that have been written, while allowing normal operation in sub-blocks that haven't been written, thereby maintaining data integrity across the entire memory string.
2Reliability
If verification level is increased to prevent threshold voltage distribution expansion, then data integrity is improved, but writing operation complexity increases
Solution Approach 1:
The verification level is made dynamic rather than fixed. The control circuit adjusts the verification level based on the writing history of each sub-block. For sub-blocks that have been previously written, a higher verification level is applied to prevent threshold voltage expansion. For sub-blocks that haven't been written, a standard verification level is used. This dynamic adjustment maintains data integrity while avoiding unnecessary complexity in writing operations.
Solution Approach 2:
The control circuit uses flag cells to store information about whether each sub-block has been previously written. This feedback mechanism allows the control circuit to automatically adjust verification levels based on writing history, eliminating the need for manual intervention or complex control logic, thus maintaining data integrity without significantly increasing writing operation complexity.
Data Source
AI summary
A memory cell array includes a plurality of memory strings divided into a plurality of sub-blocks, each memory string including a plurality of memory cells which are connected to word lines and each sub-block being erasable independently with respect to the other sub-blocks. During writing, a control unit changes a verification level to be applied to a selected word line included in a selected sub-block depending on whether or not data has been written in a non-selected sub-block.