Read-Only Memories TRIZ Cases

Simultaneous activation of normal and redundant memory region signals cuts manufacturing costs by reducing total test time for faulty cell identification.

A semiconductor memory controller applies read voltage to multiple word lines during search operations.

A switch matrix capacitor couples reverse polarity voltage to random access memory for rapid data destruction.

A memory controller adjusts program loop limits based on detected device temperature to optimize write operations.

A semiconductor memory device uses a control circuit to set multiple threshold voltages for efficient data operations.

A semiconductor memory device applies sequential discharge control voltage to remove trapped electrons from vertical channel layers.

A semiconductor memory program voltage control method adjusts threshold voltages through step-wise level reduction.

NOP columns monitor wordline programming cycles in NAND flash memory, preventing data errors from over-time programming by limiting write operations.

Segmenting verify voltages based on adjacent cell logic states compensates threshold voltage variations caused by coupling effects, maintaining data integrity.

A non-volatile memory circuit connects zener zap device cathodes to a shared power supply for both writing and reading operations.

Page buffer circuits merge internal data lines into a dynamic data bus, reducing parasitic capacitances and improving data transfer speeds.

Monotonic word line programming sequences reduce interference and preserve data integrity during high-density storage operations.

Grouping memory pages by program time enables targeted test reads to detect errors, reducing read failures in high-density NAND flash.

A memory controller detects changes in reference data stored in latch units to trigger setup data reloading from the cell array.

A nonvolatile memory controller identifies unstable erased cells by comparing threshold voltages to prevent write operation failures.

A semiconductor memory device applies distinct voltage levels to bit lines during program operations.

A voltage boosted circuit generates a high-magnitude erase pulse to permanently destroy data in NAND flash memory blocks.

Sequential sensing operations adjust read voltages based on threshold voltage valleys, reducing errors caused by program and read disturbances.

Encoding program bits partitions data to minimize adjacent zero-bit states, reducing thermal interference between phase change memory cells.

A nonvolatile memory reading method applies differentiated voltage levels to adjacent and remote cells for accurate state detection.

Dynamic verification levels applied to segmented sub-blocks narrow threshold voltage distribution, preventing data integrity loss from back pattern noise.

Non-binary address decoding reorganizes memory sections to improve layout area efficiency and reduce power consumption compared to binary designs.

Copying data to a second block allows changing patterns during refresh, reducing cumulative stress on memory cells.

A read method isolates the selected memory cell response using discrepancy calculations to determine logical states.

A semiconductor memory device stores failed column addresses in an extra block to enable post-packaging updates.

A clock control unit restricts the toggling period of a pumping control clock to generate stable internal voltage.

Sub-soft program operations narrow the threshold voltage distribution of select transistors, preventing leakage current after erase cycles.

Control logic increases cell threshold voltage via selective overwrites based on valid data quantity to maintain retention characteristics.

A semiconductor memory device uses a power-up signal generator and initializer to produce control signals for memory cell arrays.

A controller adjusts programming voltage dynamically across word lines to optimize memory cell threshold distribution.

External voltage pad supplies high current to write drivers, bypassing internal generator limits that slow set operations.

A multi-plane flash memory data transfer scheme programs parallel channels into a first plane while caching subsequent plane data in page buffers.

A non-volatile memory device generates a lock enable signal to inhibit access to data stored in the secure block during initialization.

A leakage detector measures charged voltage on designated word lines after program voltage application to identify defects.