Semiconductor Memory Device Multi-Voltage Verify Control

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Solution Overview

Problem

Semiconductor memory devices face challenges in ensuring reliable data storage due to deviations in threshold voltage distributions of memory cell transistors, which can be exacerbated by increased step-up widths of program voltages, leading to potential interference between write states and reduced reliability.

Innovation Solution

The semiconductor memory device employs a multi-voltage approach by setting three types of verify voltages (VL1, VL2, and VH) for each write state, distinguishing between fast and slow cells, and applying specific program conditions based on these voltages to control the threshold voltage increase, thereby reducing deviations and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If increased step-up widths of program voltages are used, then programming speed is improved, but threshold voltage distribution deviation increases and reliability deteriorates

Engineering Contradiction:
Improveprogramming speedVSAvoiddata storage reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent segments the verify operation into multiple stages by applying different verify voltages (first verify voltage, second verify voltage, third verify voltage) at different program loops. This segmentation allows the programming process to handle different threshold voltage ranges separately, maintaining reliability even with increased step-up widths by verifying threshold voltages in incremental stages rather than a single step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent dynamically changes verify voltage parameters during the programming process. Different verify voltages are applied at different program loops based on the current programming state. This parameter change strategy allows the system to adapt to the evolving threshold voltage distribution, ensuring accurate verification at each stage while maintaining overall reliability despite larger voltage step-ups.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If multiple verify voltages are applied at each program loop, then threshold voltage control precision is improved, but device complexity increases

Engineering Contradiction:
Improvethreshold voltage control precisionVSAvoidverify operation complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the verify operation into distinct segments corresponding to different program loops, with each loop using appropriately tailored verify voltages. This segmentation reduces complexity by assigning specific verify voltages to specific programming stages, rather than requiring all verify voltages to be managed simultaneously in a single complex operation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary verify operations with appropriate verify voltages at each program loop before proceeding to the next programming stage. This preliminary action ensures that threshold voltage control is established incrementally, preventing the need for complex post-processing or corrective operations, thereby simplifying the overall control mechanism.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If verify operations are simplified, then processing performance is improved, but threshold voltage verification accuracy may deteriorate

Engineering Contradiction:
Improveprocessing performanceVSAvoidthreshold voltage verification accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent changes verify voltage parameters dynamically across different program loops, using lower verify voltages in early loops and higher verify voltages in later loops. This parameter evolution allows the verify operation to remain relatively simple at each individual loop while collectively achieving high verification accuracy across the complete programming sequence, thus maintaining both productivity and precision.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11810629B2Semiconductor memory device
Publication Date: 2023.11.07 KIOXIA CORP
  • US11810629B2 patent drawing
  • US11810629B2 patent drawing
  • US11810629B2 patent drawing

AI summary

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.