Semiconductor Memory Device Write Speed Optimization
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Solution Overview
Problem
NAND type flash memory devices face challenges in increasing write speed due to the need for precise control of threshold voltage distributions to store multiple bits in a single cell, which requires repeated program and verify operations, leading to reduced write speed and increased power consumption.
Innovation Solution
A semiconductor memory device with a memory cell array, select transistors, and a control circuit that sets multiple threshold voltages for each memory cell, allowing for efficient data write, read, and erase operations by optimizing the potentials of word lines and bit lines, and using negative voltages to manage unselected word lines during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored in a single cell by setting multiple threshold voltages, then memory capacity is improved, but the number of program and verify operations increases, reducing write speed
Solution Approach 1:
The patent changes the parameter of threshold voltage distribution width to resolve the contradiction. By widening the threshold voltage distribution width, the patent reduces the number of program and verify operations needed, thereby improving write speed while maintaining the ability to store multiple bits in a single cell
2Quantity of substance
If threshold voltage distribution width is reduced to store more bits in a single cell, then memory capacity is improved, but write speed is reduced due to precise repetition of program and verify operations
Solution Approach 1:
The patent changes the parameter of threshold voltage distribution width from narrow to wide. This parameter change allows the system to store multiple bits in a single cell without requiring the precise repetition of program and verify operations, thereby reducing write time while maintaining high memory capacity
3Quantity of substance
If multiple threshold voltages are set in a narrow distribution to store multivalue data, then storage density is improved, but the complexity of controlling threshold distributions increases
Solution Approach 1:
The patent changes the parameter of threshold voltage distribution width to widen it. This simplifies the control of threshold distributions by reducing the number of precise control steps required, while still achieving high storage density through the ability to set multiple threshold voltages in each cell
Data Source
AI summary
A memory cell array has a plurality of series connected memory cells connected to word lines and bit lines and arranged in a matrix. A select transistor selects from the word lines. A control circuit controls potentials of the word lines and bit lines in accordance with input data, and controls a data write operation, a data read operation, and a data erase operation executed on the memory cells. The select transistor is formed on a substrate. For a read operation, the substrate is supplied with a first negative voltage, a selected word line is supplied with a first voltage (first voltageā§first negative voltage), and unselected word lines are supplied with a second voltage.