Semiconductor Select Transistor Leakage via Sub-Soft Program
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Solution Overview
Problem
Nonvolatile semiconductor memory devices face challenges in narrowing the threshold voltage distribution of select transistors, dummy cells, and memory cells after an erase operation, which can lead to increased leakage current and reduced reliability.
Innovation Solution
A semiconductor device and operating method that perform a sub-soft program operation on erased memory cells, applying specific sub-soft program voltages to select lines and dummy lines to increase the threshold voltage of select transistors and memory cells within a range below the erase level, thereby narrowing the threshold voltage distribution and preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an erase operation is performed on memory cells, then the memory cells can be reset to a known state, but the threshold voltage distribution of select transistors and dummy cells becomes widened, leading to increased leakage current
Solution Approach 1:
The patent applies a sub-soft program operation immediately after the erase operation to preliminarily adjust the threshold voltage distribution of select transistors and dummy cells before the main program operation. This preliminary action narrows the threshold voltage distribution and prevents leakage current during subsequent operations.
Solution Approach 2:
The patent changes the threshold voltage parameter of select transistors and dummy cells by applying a sub-soft program voltage. This parameter change narrows the threshold voltage distribution and ensures proper operation during program and read operations, directly addressing the leakage current issue.
2Productivity
If a standard program operation is performed after erase, then data can be written to memory cells, but leakage current occurs due to widened threshold voltage distribution of select transistors
Solution Approach 1:
The patent performs a sub-soft program operation as a preliminary step before the main program operation. This preliminary action adjusts the threshold voltage distribution of select transistors to prevent leakage current during the subsequent main program operation, ensuring both productivity and reliability.
Solution Approach 2:
The patent maintains continuous useful action by performing the sub-soft program operation immediately after erase and before the main program operation. This continuous adjustment of threshold voltage ensures that select transistors remain in an optimal state throughout the operation sequence, preventing leakage current while maintaining operation efficiency.
3Reliability
If the threshold voltage of select transistors is increased to prevent leakage, then reliability improves, but the complexity of the programming operation increases
Solution Approach 1:
The patent segments the programming operation into two distinct steps: a sub-soft program operation to adjust threshold voltage distribution, and a main program operation to write data. This segmentation allows the threshold voltage adjustment to be performed separately and efficiently, improving select transistor performance without excessively complicating the overall programming operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The sub-soft program operation effectively narrows the threshold voltage distribution of select transistors and memory cells, enhancing the reliability of the semiconductor device by preventing leakage current and ensuring proper operation.
Implementation Method 1
increasing a threshold voltage of the select transistors within a range below an erase level, and increasing the threshold voltage of the select transistors up to a program level
Data Source
AI summary
A semiconductor device includes memory blocks including a plurality of strings in which memory cells are coupled between select transistors; a peripheral circuit suitable for erasing or programming the select transistors and the memory cells, which are included in a selected memory block among the memory blocks; and a control circuit suitable for controlling the peripheral circuit to erase the select transistors and the memory cells, increasing a threshold voltage of the select transistors within a range below an erase level, and increasing the threshold voltage of the select transistors up to a program level.