Wordline Smart Tracking Verify for 3D Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face inefficiencies in programming and verify operations due to the time-consuming nature of verify tests, especially with a large number of data states, which can lead to unnecessary tests and increased programming time.
Innovation Solution
The implementation of an adaptive approach where the controller determines the optimal programming voltage by incrementally adjusting the voltage during program-verify iterations, skipping unnecessary verify tests based on the progress of memory cells and their threshold voltage distribution, and applying a smart verify scheme across groups of memory cells at different heights in a 3D memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verify tests are performed for all memory cells with a large number of data states, then programming completeness is ensured, but programming time increases significantly
Solution Approach 1:
The patent changes the verify voltage parameter dynamically based on the data state being programmed. Different verify voltages are applied for different data states (e.g., first verify voltage for first data state, second verify voltage for second data state), allowing the system to optimize verify operations for each specific state rather than using a fixed verify approach for all states.
Solution Approach 2:
The patent segments the verify operation by data state. Instead of performing a single comprehensive verify test that checks all data states equally, the verify process is divided into separate verify operations for each data state, with each verify operation using optimized parameters specific to that state. This segmentation allows unnecessary verifies to be skipped.
2Manufacturing precision
If verify tests are performed frequently to ensure programming accuracy, then programming precision is improved, but the number of verify tests increases and time is lost
Solution Approach 1:
The patent applies partial verify action by performing verify tests only on the specific data state that is currently being programmed, rather than performing excessive full verifies that check all data states. This partial action approach maintains programming accuracy for the target state while avoiding redundant verify operations on other states.
Solution Approach 2:
The patent makes the verify operation dynamic by adapting the verify voltage and verify timing based on the current programming state. The verify scheme transitions from static fixed verify to dynamic adaptive verify, where verify parameters change according to the programming progress and data state, optimizing both accuracy and speed.
3Device complexity
If a fixed verify voltage is used for all data states, then device complexity is reduced, but programming precision deteriorates due to inability to optimize for different states
Solution Approach 1:
The patent applies local quality by using different verify voltages for different data states. Instead of a uniform verify voltage applied globally to all states, each data state has its own optimized verify voltage (first verify voltage for first data state, second verify voltage for second data state), allowing precise verification tailored to each state's characteristics.
Solution Approach 2:
The patent creates a multi-functional verify scheme where the verify circuit can operate with multiple different verify voltages depending on the data state. The verify mechanism serves multiple functions by adapting to different programming scenarios, maintaining precision across various data states while using a unified control approach.
Data Source
AI summary
The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.