Semiconductor Memory Device Discharge Control Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face reliability issues due to trapped electrons in vertical channel layers, which affect read, program verification, and erase verification operations, leading to inconsistent sensing operations.
Innovation Solution
A semiconductor memory device and operating method that involves a peripheral circuit to successively apply a discharge control voltage to memory cells in sequence from the source select transistor to the drain select transistor, effectively discharging trapped electrons and holes before performing read or verification operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read, program verification, and erase verification operations are performed without discharging trapped electrons, then the operations can be executed quickly, but the reliability and consistency of sensing operations deteriorate
Solution Approach 1:
The patent applies a discharge control voltage to memory cells before performing read, program verification, or erase verification operations to remove trapped electrons from the channel layer. This preliminary discharge action ensures that no residual charges interfere with the sensing operation, thereby improving reliability without significantly impacting overall operation time since the discharge occurs in a controlled sequence before the actual sensing begins
2Measurement precision
If a discharge control voltage is applied to memory cells, then trapped electrons are discharged improving sensing accuracy, but the device complexity increases due to additional control circuitry
Solution Approach 1:
The discharge control voltage mechanism is integrated into the existing word line control structure, allowing the same control circuitry to serve both normal read operations and discharge operations. The control logic repurposes existing voltage generation and distribution pathways to apply discharge control voltages through word lines, rather than requiring entirely separate dedicated discharge circuitry, thereby limiting the increase in device complexity
3Reliability
If discharge control voltage is applied sequentially from source select transistor to drain select transistor, then all trapped electrons are fully discharged improving consistency, but the operation duration increases
Solution Approach 1:
The discharge control voltage is applied in a sequential periodic manner across different memory cells, moving from those adjacent to the source select transistor toward those adjacent to the drain select transistor. This systematic progression ensures thorough discharge of trapped electrons across all relevant memory cells while maintaining a structured timing pattern that optimizes the balance between complete discharge and operation duration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the reliability of sensing operations by ensuring that electrons and holes are fully discharged, enhancing the accuracy and consistency of read, program verification, and erase verification operations.
Implementation Method 1
applying the discharge control voltage to the memory cells in sequence from a memory cell adjacent to the source select transistor to a memory cell adjacent to the drain select transistor
Data Source
AI summary
Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include: drain select transistor coupled to a bit line; a source select transistor coupled to a source line; a plurality of memory cells coupled in series between the drain select transistor and the source select transistor; and a peripheral circuit configured to successively apply a discharge control voltage to memory cells in sequence from a memory cell adjacent to the source select transistor to a memory cell adjacent to the drain select transistor.