Page Buffer Circuits Reducing Parasitic Capacitance
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Solution Overview
Problem
The size of memory devices is limited by the footprint of the data bus that transfers data from page buffers in page buffer circuits, and memory speed is hindered by parasitic capacitances during data transfer.
Innovation Solution
The implementation of page buffer circuits where internal data lines (IDLs) of page buffers are conductively connected to form a data bus (DBUS) for data transfer, allowing for the configuration of connection transistors to connect or separate IDLs, thereby managing data bus length and reducing parasitic capacitances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a separate data bus is provided to transfer data from page buffers, then data transfer function is achieved, but the footprint area increases and memory device size is limited
Solution Approach 1:
The patent combines the data bus function with existing internal data lines (IDLs) of the page buffers. Instead of providing a separate dedicated data bus, the IDLs are conductively connected together to form the data bus, merging two functions into a single structure and reducing the overall footprint area.
Solution Approach 2:
The internal data lines (IDLs) serve dual purposes: they function as internal connections within page buffers and simultaneously serve as the data bus for data transfer. This multi-functionality eliminates the need for separate data bus structures, reducing area while maintaining data transfer capability.
2Productivity
If data bus length is increased to connect all page buffers, then data transfer coverage is improved, but parasitic capacitances increase and memory speed is limited
Solution Approach 1:
The data bus is segmented into multiple sections, each corresponding to a page buffer's internal data line. Connection transistors are used to selectively connect or disconnect these segments, allowing the data bus to be divided into smaller active sections during different operations, thereby reducing total parasitic capacitance while maintaining coverage capability.
Solution Approach 2:
The data bus configuration is made dynamic through connection transistors that can selectively connect or disconnect IDLs based on operational requirements. This dynamic reconfiguration allows the system to optimize between coverage and parasitic capacitance by activating only the necessary segments during each operation.
Data Source
AI summary
A memory device includes a memory cell array including memory cells; a page buffer circuit including a plurality of page buffers coupled to the memory cell array, each page buffer including a plurality of latches and an internal data line (IDL) arranged to couple to the plurality of latches; and a cache circuit including a plurality of caches. The IDLs of the plurality of page buffers are configured to be conductively connected together to form a data bus (DBUS) that conductively connects the page buffer circuit to the cache circuit for data transfer.