Non-Binary Memory Address Decoding for Area and Power Optimization
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Solution Overview
Problem
The existing semiconductor memory array designs that facilitate binary address decoding limit flexibility, leading to poor layout area efficiency and compromised performance due to electrical characteristics, resulting in slower memory cell access times and higher power consumption.
Innovation Solution
The semiconductor device incorporates a flexible memory address decoding system that allows for non-binary arrangements of memory banks and sections, utilizing row and column decoders, sense amplifiers, and redundant address circuits to enable efficient access and repair of memory cells, while minimizing power consumption through threshold voltage compensation and strategic placement of redundant memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If binary address decoding is used to organize memory banks and sections, then address decoding simplicity is improved, but layout area efficiency and performance deteriorate
Solution Approach 1:
The patent changes the fundamental parameter of address decoding from binary to non-binary (specifically ternary/tri-state) decoding. This allows memory sections to be organized in groups of three rather than powers of two, enabling more efficient packing of memory cells into the available layout area and improving overall area efficiency while maintaining decoding simplicity through the use of specialized decoder circuits.
2Device complexity
If binary address decoding is used to organize memory banks and sections, then address decoding simplicity is improved, but access time performance deteriorates
Solution Approach 1:
The patent implements non-binary address decoding that reorganizes memory access patterns, allowing for optimized row and column selection that reduces access time. By grouping memory sections in non-binary configurations, the decoder can more efficiently select and access specific memory cells, thereby improving access time performance while keeping the decoding mechanism relatively simple through dedicated circuitry.
3Device complexity
If binary address decoding is used to organize memory banks and sections, then address decoding simplicity is improved, but power consumption increases
Solution Approach 1:
The patent employs non-binary address decoding that optimizes the activation patterns of memory sections and associated circuitry. By organizing memory in non-binary groups, the system can more selectively activate only the necessary rows and columns for each access operation, reducing the number of simultaneously active circuits and thereby lowering overall power consumption while maintaining decoding simplicity through specialized decoder design.
Data Source
AI summary
Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.