Memory Device Parallel Test Mode Reduces Manufacturing Time
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Solution Overview
Problem
The existing memory device testing process is time-consuming and increases manufacturing costs due to the need for separate tests on normal and redundant memory regions, which can be inefficient in identifying and addressing faulty memory cells.
Innovation Solution
A memory device with an address decoder that simultaneously activates normal and redundant memory region signals during a test mode, allowing for parallel testing of both regions to reduce overall test time and identify faulty cells more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate tests are performed on normal and redundant memory regions, then testing thoroughness is improved, but test time increases
Solution Approach 1:
The patent combines the testing of normal and redundant memory regions into a single simultaneous test operation. The address decoder is configured to generate both normal memory region signals and redundant memory region signals at the same time when in test mode, allowing both regions to be tested in parallel rather than sequentially, thus reducing total test time while maintaining thoroughness
Solution Approach 2:
The address decoder dynamically switches between normal operation mode and test mode. In test mode, it simultaneously activates signal generators for both normal and redundant memory regions, enabling the system to adapt its behavior based on operational requirements and achieve efficient parallel testing without compromising reliability
2Measurement precision
If separate tests are performed on normal and redundant memory regions, then fault identification accuracy is improved, but manufacturing cost increases
Solution Approach 1:
By merging the test operations for normal and redundant memory regions into a single simultaneous process, the patent reduces manufacturing costs associated with extended testing time while maintaining fault identification accuracy through the coordinated activation of signal generators for both regions
3Loss of time
If simultaneous tests are performed on normal and redundant memory regions, then test time is reduced, but device complexity increases
Solution Approach 1:
The address decoder is designed with multi-functionality to handle both normal memory region signaling and redundant memory region signaling within a single device. This universal design enables simultaneous testing of both regions without requiring separate testing equipment or additional external components, thus reducing overall system complexity despite the enhanced functionality
4Ease of manufacture
If simultaneous tests are performed on normal and redundant memory regions, then manufacturing cost is reduced, but signal coordination complexity increases
Solution Approach 1:
The address decoder's universal design integrates multiple signal generation functions into a single coordinated unit. It simultaneously generates normal memory region signals and redundant memory region signals with proper timing and sequencing, eliminating the need for separate testing operations and reducing manufacturing costs associated with extended test times and additional equipment
Data Source
AI summary
A memory device includes memory cell array and an address decoder. The memory cell array includes a normal memory region and a redundant memory region. The normal memory region operates in response to data signal and plurality of normal memory region signals. The redundant memory region operates in response to data signal and plurality of redundant memory region signals. The address decoder includes normal memory region signal generator and redundant memory region signal generator. The normal memory region signal generator activates first normal memory region signals and redundant memory region signal generator activates first redundant memory region signal simultaneously when address decoder operates in test mode. First normal memory region signals correspond to an address signal and are included in plurality of normal memory region signals. A first redundant memory region signal corresponds to an address signal and is included in the plurality of redundant memory region signals.