Semiconductor Memory Program Voltage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing methods for operating semiconductor memory devices, particularly NAND flash memory devices, face challenges in increasing the speed of program operations and improving electrical characteristics and reliability due to errors caused by voltage changes during program operations, especially when raising threshold voltages of memory cells to different levels.

Innovation Solution

A method involving the gradual reduction of program voltage levels from a third level to a first level on selected word lines, discharging bit lines, and supplying program inhibition voltages to other bit lines, while coupling cell strings to bit lines and precharging channel regions to manage voltage levels effectively, thereby optimizing the program operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple program pulses are supplied to raise threshold voltages to different levels, then data storage capacity is improved, but program operation time increases

Engineering Contradiction:
Improvedata storage capacityVSAvoidprogram operation time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent applies periodic action by using a single program pulse with periodically varying voltage levels instead of multiple separate pulses. The voltage level changes periodically during the pulse duration to achieve different threshold voltage levels, thereby reducing program operation time while maintaining data storage capacity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent employs dynamics by making the program voltage level variable during the pulse operation. The voltage level dynamically changes from a first level to a second level and optionally to a third level within the single pulse, allowing different memory cells to reach different threshold voltage levels simultaneously, thus reducing overall program time.

Inventive Principle:
Principle #15Dynamics

2Speed

If program voltage is supplied to raise threshold voltages quickly, then program speed is improved, but voltage control precision deteriorates

Engineering Contradiction:
Improveprogram speedVSAvoidvoltage control precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent uses periodic action to maintain voltage control precision during fast programming. The voltage level changes periodically at specific time points during the pulse, allowing controlled transitions between different voltage levels while maintaining overall program speed. This periodic modulation ensures precise voltage control for different threshold voltage targets.

Inventive Principle:
Principle #19Periodic action

3Productivity

If channel voltage is discharged to raise threshold voltages, then program operation is improved, but errors occur due to voltage changes

Engineering Contradiction:
Improveprogram operation efficiencyVSAvoidprogram operation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary anti-action by precharging the channel voltage to a specific level before the program pulse is applied. This precharging creates a voltage state that counteracts the harmful voltage changes during programming, preventing errors while allowing efficient threshold voltage adjustment. The precharged channel voltage serves as a buffer against unwanted voltage fluctuations.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS8681544B2Method of operating semiconductor memory device
Publication Date: 2014.03.25 SK HYNIX INC
  • US8681544B2 patent drawing
  • US8681544B2 patent drawing
  • US8681544B2 patent drawing

AI summary

A method of operating a semiconductor memory device includes applying a program pass voltage to unselected word lines, applying a program voltage of a third level to a selected word line in order to raise threshold voltages of third memory cells, decreasing a level of the program voltage from the third level to a second level and discharging channel regions of second cell strings including second memory cells in order to raise threshold voltages of second memory cells, and decreasing a level of the program voltage from the second level to a first level and discharging channel regions of first cell strings including first memory cells in order to raise threshold voltages of first memory cells. The cell strings are disconnected from a bit line while a voltage level of the unselected word lines rises to a level of the program pass voltage.