3D NAND Sub-BSG Structure for Faster Erase and Data Transfer
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Solution Overview
Problem
As 3D NAND technology advances towards higher density and capacity, the increasing number of word line layers leads to longer read and erase times, longer data transfer times, and lower storage efficiency due to the shared bottom select gate (BSG) controlling all memory cell strings in a block simultaneously.
Innovation Solution
The 3D NAND memory device employs a divided block structure by separating the shared BSG into sub-BSGs through dielectric trenches, allowing each sub-block to be operated individually. This structure reduces parasitic capacitance and coupling effects, improving the performance of bottom select transistors and enabling faster erasing and data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fabrication processes are used for planar NAND flash memory, then manufacturing simplicity is maintained, but memory density and storage capacity are limited
Solution Approach 1:
The patent transitions from planar (2D) NAND flash memory architecture to three-dimensional (3D) stacked architecture. Multiple memory cell layers are vertically stacked above the substrate, with word lines and control gates arranged in three dimensions. This dimensional transition enables significantly higher memory density by utilizing vertical space rather than only horizontal plane area.
Solution Approach 2:
The memory structure is divided into multiple discrete layers including first memory cell layers, second memory cell layers, charge trap layers, blocking insulating layers, and tunnel insulating layers. Each layer is formed through separate fabrication processes, allowing independent optimization and control of specific memory functions while managing overall device complexity.
2Quantity of substance
If memory cell layers are stacked vertically to increase density, then storage capacity improves, but fabrication precision and alignment requirements worsen
Solution Approach 1:
Trench isolation structures are formed in the substrate before stacking memory cell layers. These pre-formed trenches provide physical boundaries and alignment references that guide subsequent layer formation processes, ensuring precise positioning of vertically stacked layers and maintaining manufacturing precision throughout the 3D assembly process.
Solution Approach 2:
Blocking insulating layers and tunnel insulating layers are introduced as intermediary structures between memory cell layers. These intermediary layers serve as spacing elements and alignment references, facilitating precise positioning of adjacent memory cell layers while enabling vertical stacking for increased storage capacity.
3Quantity of substance
If more memory layers are stacked to increase capacity, then storage density improves, but process time and manufacturing duration worsen
Solution Approach 1:
The fabrication process employs continuous thin film deposition techniques to form multiple memory cell layers, insulating layers, and conductive layers without interruption. This continuous processing approach maintains production flow efficiency while building complex 3D structures, reducing total fabrication time compared to discrete batch processing of each layer.
Solution Approach 2:
Trench isolation structures and preliminary substrate preparations are formed before the main stacking process begins. This preliminary action establishes a prepared foundation that accelerates subsequent layer formation by providing pre-defined boundaries and alignment features, reducing overall process time despite increased layer count.
Data Source
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Figure 1B
Figure 1C-1~1D-2
AI summary
A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.