3D NAND Memory Top Poly Cut for High Density Stacking
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Solution Overview
Problem
The scalability and efficiency of 3D NAND memory devices are limited by the need for deep slit etching, which increases the pitch between elements and reduces array density as more layers are stacked.
Innovation Solution
A novel 3D structure is implemented with only a top poly cut to bypass process window limitations, allowing for higher stacking efficiency without extending cuts into bottom layers, thereby enhancing array density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If deep slit etching is performed to stack more layers, then the number of layers increases, but the pitch between elements increases and array density decreases
Solution Approach 1:
The patent divides the etching operation into two separate stages: first etching the word line layers to a first depth, then etching the select line layer to a greater second depth. This segmentation allows each etching step to be optimized independently, avoiding the need for a single deep etch that would increase pitch, thereby maintaining smaller pitch between elements while achieving higher layer stacking.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional vertically-stacked structure by stacking multiple layers of word lines and select lines vertically. This dimensional change increases the number of memory cells per unit area, improving array density without requiring increased pitch between elements.
2Volume of moving object
If deep slit etching is performed to increase layer stacking, then more layers can be stacked, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The manufacturing process is segmented into distinct etching steps with different depths and selectivities. The first etching step targets word line layers to a specific depth, while the second etching step targets the select line layer to a greater depth. This segmentation simplifies each individual etching step, making the overall manufacturing process more controllable and less complex than performing a single deep etch.
Solution Approach 2:
The patent applies different etching conditions and selectivities to different regions and layers. The first etching step uses parameters optimized for word line layers, while the second etching step uses parameters optimized for the select line layer. This local optimization of etching quality reduces process difficulty and improves manufacturing ease.
3Quantity of substance
If more layers are stacked to increase density, then array density improves, but the number of elements horizontally oriented decreases
Solution Approach 1:
The patent resolves this contradiction by moving elements from a horizontal arrangement to a vertical stack configuration. Multiple word line layers and select line layers are stacked vertically, with each layer containing memory cells that connect to bit lines. This vertical stacking increases the quantity of memory cells (array density) without reducing the number of horizontal bit line connections.
Solution Approach 2:
The patent segments the memory array into multiple vertical stacks, each containing multiple layers of memory cells. Each stack is independently connected to bit lines through select lines, allowing the horizontal connectivity to be maintained while increasing vertical density. This segmentation enables both high array density and sufficient horizontal element connectivity.
Data Source
AI summary
Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n−1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.