3D NAND Memory Temporary Read Error Mitigation
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Solution Overview
Problem
Three-dimensional (3D) NAND memory devices experience temporary read errors (TRE) due to high fail bit count during the first read operation after recovering from an idle state, leading to reduced random read performance and Quality of Service (QoS) deterioration.
Innovation Solution
A memory device with a controller that determines if a read operation is the first read after an idle state, and if so, performs an extended pre-phase before the read-phase, involving ramping up and down selected word lines and select gates to a read pass voltage, with specific time durations to alleviate TRE without using a virtual read operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a virtual read operation is performed to alleviate temporary read errors, then reliability is improved, but loss of time increases
Solution Approach 1:
The patent applies preliminary action by extending the pre-phase of the first read operation to occur before the actual read-phase. This extended pre-phase prepares the memory device by activating word lines and select gates in advance, which reduces temporary read errors without requiring a separate virtual read operation, thus avoiding the time penalty associated with traditional preliminary read approaches
2Reliability
If the pre-phase time duration is extended to reduce temporary read errors, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent applies dynamics by making the pre-phase time duration adaptive rather than fixed. The controller dynamically adjusts the pre-phase duration based on whether it is the first read operation after an idle state, allowing the system to optimize between reliability and productivity by extending time only when necessary to alleviate temporary read errors
3Loss of substance
If memory device size is reduced to decrease manufacturing cost, then loss of substance decreases, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar memory cell architecture to three-dimensional stacked architecture. This vertical stacking approach increases storage density without requiring proportional increases in manufacturing precision, as the 3D structure allows for more cells per unit area while maintaining feasible fabrication processes
Data Source
AI summary
Systems, methods and media of optimization of temporary read errors (TRE) in three-dimensional (3D) NAND memory devices are disclosed. A disclosed memory device can comprises a plurality of memory cells arranged as an array of NAND memory strings, a plurality of word lines couple to the memory cells, and a controller. The controller is configured to determine whether a next read operation is a first read operation of the memory device after recovering from an idle state, and In response to a positive result of the determination, control the memory device to perform an extended pre-phase of the first read operation before a read-phase of the first read operation.