Read-Only Memories TRIZ Cases

A skew signal generator encodes fuse data to adjust delay intervals in semiconductor memory circuits.

Segmented capacitive elements and extraction of leakage paths improve write yield by maintaining more negative boost voltage.

A multi-deck memory device places buffer circuitry under the array to support separate data lines for each deck.

A monitoring cell within a NAND flash memory string detects read disturb conditions through differential voltage application.

A memory controller manages row hammer disturbances by selecting target addresses based on access counts and performing adjacent refresh operations.

A semiconductor memory device applies specific voltage combinations to interconnects via a control circuit.

Floated bit lines and ramp signals lower power consumption while maintaining consistent programming speed across memory cells.

Shared column decoders reduce circuit area and power consumption by merging data input circuits across multiple memory banks.

A sense amplifier uses dynamic and static data latches to manage bit line voltages.

A dual power domain architecture supplies distinct voltage levels to bit line drivers and latches within NAND flash sensing circuitry.

Parallel shift reads across planes reduce data retrieval time while maintaining measurement precision for accurate voltage optimization.

Segmented SLC NAND planes with ternary CAM cells execute parallel searches to increase throughput and reduce latency for large key datasets.

Staged source select voltage transitions disperse peak current during programming, resolving energy concentration trade-offs in memory blocks.

Non-volatile RRAM in the cache register maintains data across power cycles, solving area and reliability issues in NAND flash page buffers.

A potential control unit manages bit line voltage levels to enable single-step programming of multi-level cell memory arrays.

A check circuit monitors internal synchronization signals to generate toggle-based verification data for memory read operations.

Segmenting the program pulse into lower and higher levels minimizes tunnel oxide damage while maintaining programming speed.

Shift registers generate select signals to activate program circuits, resolving limited data capacity in traditional fuse ROM techniques.

Adjusting verify voltage based on cell count differences compensates for quick charge loss in flash memory programming.

Segmented Huffman encoding compresses defective address lists to minimize storage space in NAND flash memory arrays.

Applying pseudo-randomization to flash memory data patterns prevents persistent bit sequences that cause program disturbs and floating gate coupling.

A NAND flash controller adjusts program voltage after resume based on suspend duration.

An amplifying circuit boosts low read currents for accurate state judgment, preventing misjudgment at reduced voltages.

A memory cell interference measurement method detects low frequency noise in cell current to quantify charge trap effects.

Applying negative bitline biasing to specific memory cells reduces program and verify execution time while maintaining programming reliability.

Delaying the program bit line boost accounts for RC delays on the inhibit bit line, reducing program disturb in NAND flash memory.

A flash memory voltage generator adjusts read voltage levels based on supply conditions to maintain stable cell thresholds.

A pipe register control signal generation circuit uses a duplicate sense amplifier to simulate primary sensing operations.

A storage controller detects ungraceful shutdown events and issues block busy alerts to the host device.

A semiconductor device uses a differential amplifier circuit with a variable current source to control bit line voltage.

A 3D NAND memory controller executes an extended pre-phase before the first read operation after an idle state to prepare word lines and select gates.

A system controller writes data to a flash memory die's lower page before its upper page.

Reduced erase bias identifies least erased bits to prevent over-erasure of fast cells during non-volatile memory production testing.

A charge and discharge detector monitors bus voltage levels to control precharge operations in semiconductor storage devices.

Current sensing circuits monitor total die current during programming to verify cell states without time-consuming scan operations, reducing power consumption.

Antifuse memory array circuit architecture reduces current delivery needs and eliminates high-voltage exposure, resolving design complexity trade-offs.

Dynamic voltage bin assignment reduces latency by prioritizing scans for younger blocks.

Dynamic source voltage adjustment increases sensing margin and operating speed while reducing leakage current errors in low-voltage memory applications.

Dividing the memory array into sub-arrays allows one sense amplifier to service multiple groups sequentially, reducing die size and power consumption.

A refresh address control circuit detects frequent row access patterns to trigger targeted memory refresh operations.

Downward protrusions in buried source lines neutralize positive charge accumulation during anisotropic etch, preventing arcing between the line and substrate.

Distinct dummy pass voltages program dummy cells to suppress gate-induced drain leakage and hot electron injection during normal cell operations.

Column control circuits perform LM address scans to detect flag data presence in memory cores.

A shared block decoder manages defective memory cell groups using a signal retention circuit and determination circuit to reduce manufacturing cost.

A storage controller correlates program voltages across nonvolatile memory cell groups using a unified verification word line to accelerate data writing.

Zone-based pass voltage application enlarges the voltage window, preventing program disturbance and reducing development time.

Pre-calibrates tunneling voltage profiles in RFID ICs to reduce nonvolatile memory write time and oxide stress.

Randomized refresh periods prevent oscillating behavior and resource waste while maintaining data reliability against write disturb errors.

Segmented array write operations reduce power consumption and write disturb in dense cross-point PRAM memory.

Ramping control gate voltage over ten microseconds reduces peak tunneling current and stress on memory cells, improving data retention in SLC devices.