Semiconductor Memory Device Defective Cell Isolation
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Solution Overview
Problem
Semiconductor memory devices using magnetoresistive random access memory (MRAM) face challenges in managing defective memory cells, where short-circuited switching elements can lead to unintended current flow, affecting data retention and access operations.
Innovation Solution
The implementation of a semiconductor memory device with a control circuit that applies specific voltage combinations to interconnects based on command types, utilizing a defective memory cell table to differentiate access operations for normal and defective cells, preventing current flow through defective cells during access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If voltage is applied to access memory cells, then data access is enabled, but current flows through defective cells causing data retention issues
Solution Approach 1:
The patent applies different voltage levels to different interconnects based on their connection status. Specifically, full access voltage is applied to bit lines connected to normal memory cells, while reduced or zero voltage is applied to bit lines connected to defective cells. This local differentiation of voltage quality enables fast access for normal cells while preventing harmful current flow through defective cells, thus resolving the contradiction between access speed and data retention reliability.
2Adaptability or versatility
If access voltage is applied to all bit lines, then all memory cells can be accessed, but defective cells with short-circuited switching elements cause unintended current flow
Solution Approach 1:
The patent segments the bit lines into different groups based on their connection status - bit lines connected to defective memory cells are separated from those connected to normal cells. The control circuit identifies which bit lines are connected to defective cells and applies different voltage levels to each segment. This segmentation allows the system to maintain high adaptability by accessing all normal cells while eliminating the harmful current flow from defective cells through targeted voltage suppression on specific bit line segments.
3Reliability
If defective memory cells are isolated using voltage control, then data integrity is maintained, but additional control operations are required
Solution Approach 1:
The patent performs preliminary identification and classification of defective memory cells before normal access operations. The control circuit pre-establishes knowledge of which bit lines are connected to defective cells, allowing it to automatically apply appropriate voltage levels during subsequent access operations without requiring complex real-time decision-making. This preliminary action simplifies the overall control complexity by transforming a dynamic control problem into a predetermined, automated response system that maintains data integrity through routine voltage differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables reliable data access and retention by isolating defective memory cells, ensuring normal cells are accessed without current flow through defective ones, thus maintaining data integrity and system performance.
Implementation Method 1
A semiconductor memory device according to one embodiment includes: a first memory cell and a first switching element coupled in series between a first interconnect and a second interconnect; a second memory cell and a second switching element coupled in series between the first interconnect and a third interconnect; a third memory cell and a third switching element coupled in series between the first interconnect and a fourth interconnect
Data Source
AI summary
A semiconductor memory device includes: a first memory cell and switching element coupled in series between a first and second interconnect; a second memory cell and switching element coupled in series between the first and a third interconnect; a third memory cell and switching element coupled in series between the first and a fourth interconnect; and a control circuit. The control circuit is configured to: in a first operation on the first memory cell, upon receipt of a first command, apply a third voltage between the first and second voltage to the third and fourth interconnect; and upon receipt of a second command, apply the first and third voltage to the fourth and third interconnect, respectively.