Negative Bit Line Biasing for Quick Pass Write Programming
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Solution Overview
Problem
Existing memory device programming techniques require more voltage pulses and time to achieve reliable programming, often sacrificing speed for accuracy or vice versa, leading to inefficient resource utilization.
Innovation Solution
A method involving a control circuit that performs multiple programming loops with varying bitline voltages to program memory cells at different speeds, applying a first bitline voltage to slower QPW cells and a third bitline voltage, potentially negative, to faster reverse QPW cells, while inhibiting programming of certain cells, thereby optimizing programming speed and accuracy without increasing total programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single programming voltage and bitline voltage are applied to all memory cells, then the programming process is simple to implement, but the programming speed and accuracy cannot be optimized for different cell types
Solution Approach 1:
The patent divides memory cells into different groups (first group and second group) based on their programming characteristics. Different bitline voltages are applied to different groups during programming operations, allowing optimized programming speeds for each group while maintaining a unified programming interface at the controller level.
Solution Approach 2:
The patent dynamically adjusts bitline voltages based on the programming state and requirements of different memory cell groups. The control circuit switches between different voltage levels (e.g., first bitline voltage for QPW cells, second bitline voltage for reverse QPW cells) during the programming process to optimize both speed and accuracy.
2Speed
If faster programming voltages are applied to all memory cells, then programming speed increases, but programming accuracy and reliability deteriorate
Solution Approach 1:
The patent applies different bitline voltage levels to different groups of memory cells based on their specific programming requirements. Fast programming voltages (second bitline voltage) are applied only to cells that can tolerate and benefit from rapid programming (reverse QPW cells), while slower, more accurate voltages (first bitline voltage) are applied to cells requiring precision (QPW cells). This local differentiation resolves the contradiction between speed and reliability.
3Reliability
If slower programming is applied to ensure accuracy, then programming reliability improves, but total programming time increases
Solution Approach 1:
By segmenting memory cells into different programming groups, the patent enables parallel processing where different voltage regimes can be applied simultaneously to different cell groups. This eliminates the need to slow down the entire programming operation to accommodate accuracy-critical cells, as only the necessary subset receives slower programming while others proceed at high speed.
Solution Approach 2:
The patent changes the bitline voltage parameter dynamically during programming operations based on the target data state and cell group. By switching between first bitline voltage (slower, more accurate) and second bitline voltage (faster), the system optimizes the trade-off between programming time and accuracy for each cell group, reducing total programming time while maintaining reliability.
4Productivity
If different programming speeds are applied to different memory cell groups, then resource utilization is optimized, but the programming process complexity increases
Solution Approach 1:
The control circuit is designed to handle multiple programming modes (QPW and reverse QPW) through a unified interface. The same control circuitry that manages standard programming operations also manages the differentiated voltage applications, making the system multi-functional without requiring separate dedicated circuits for each programming mode.
Solution Approach 2:
The control circuit acts as an intermediary between the controller and memory cells, translating high-level programming commands into specific voltage patterns for different cell groups. This intermediary layer abstracts the complexity of differentiated programming from the controller, maintaining simplicity at the interface while enabling complex optimized programming internally.
Data Source
AI summary
A method of operating a memory system includes a first programming loop, which includes applying a first programming voltage to a control gate of a selected word line and applying a first bitline voltage to a bitline coupled to a first memory cell that is being programmed to a first data state and to a different bitline coupled to a second memory cell that is being programmed to a second data state. In a second programming loop, a second bitline voltage is applied to the bitline coupled to the first memory cell, and a third bitline voltage is applied to the bitline coupled to the second memory cell. The second bitline voltage is greater than the first bitline voltage to reduce a programming speed of the first bitline voltage to increase a programming speed of the second memory cell.