DRAM Row Hammer Mitigation via Adaptive Refresh Control
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Solution Overview
Problem
Dynamic random access memory (DRAM) faces interference issues due to narrowing inter-cell gaps, leading to row hammer disturbances that affect data reliability and refresh characteristics, with existing technologies struggling to effectively manage diverse row hammer attack patterns.
Innovation Solution
A memory device and system that includes row address registers, count registers, and a target row refresh controller to manage row hammer disturbances by performing refresh operations based on access counts, selecting target row addresses for intensive care when counts exceed a reference value and randomly selecting addresses for care when counts do not, thereby maintaining row hammer levels below a predetermined threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the inter-cell gap is narrowed to increase integration density, then the degree of integration is improved, but row hammer disturbance increases
Solution Approach 1:
The patent performs preliminary detection of row hammer attacks by monitoring access counts to row addresses, and proactively executes refresh operations on adjacent rows before data corruption occurs. The row hammer detection unit continuously tracks access patterns and triggers preventive refresh operations when threshold values are exceeded, thereby preventing the harmful effect rather than reacting after damage occurs.
Solution Approach 2:
The patent implements a feedback mechanism where the row hammer detection unit monitors access counts and generates detection signals, which are then fed back to the refresh control unit. This closed-loop feedback system adjusts refresh operations based on real-time access patterns, dynamically responding to potential row hammer threats while maintaining normal operation under normal conditions.
2Measurement precision
If access count monitoring is performed for all row addresses, then row hammer detection accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing access count monitoring and refresh operations specifically for row addresses that exhibit suspicious access patterns indicative of row hammer attacks, rather than uniformly monitoring all row addresses. The refresh control unit selectively performs refresh operations on adjacent rows only when detection signals are generated for specific target rows, optimizing resource usage while maintaining detection accuracy.
Solution Approach 2:
The patent changes the parameter of monitoring scope dynamically based on access patterns. Instead of continuously monitoring all rows with equal intensity, the system adjusts monitoring focus to specific row addresses that exceed predefined access count thresholds, thereby reducing overall system complexity while maintaining high detection accuracy for actual attacks.
3Reliability
If intensive refresh operations are performed on adjacent rows when access count exceeds threshold, then data reliability is improved, but energy consumption increases
Solution Approach 1:
The patent applies partial action by performing refresh operations only on the specific adjacent rows that are vulnerable to row hammer attacks from a detected target row, rather than refreshing the entire memory array. When a row hammer attack is detected on a specific row, the refresh control unit selectively refreshes only the immediately adjacent rows that would be affected by capacitive coupling, thereby maintaining data reliability while minimizing unnecessary energy consumption.
Solution Approach 2:
The patent implements periodic refresh operations triggered by access count thresholds rather than continuous refreshing. The system monitors access patterns and performs intensive refresh operations only periodically when detection signals indicate potential row hammer attacks, thereby reducing overall energy consumption compared to continuous refresh while maintaining data reliability when needed.
Data Source
AI summary
A memory device includes first registers configured to store row addresses second registers configured to store an access count of each of the row addresses and generate a reference value flag signal when the access count is higher than a reference value. The memory device also includes a target row refresh controller configured to select one of the row addresses as a first target row address in response to the reference value flag signal, perform a first refresh operation on at least one first row address adjacent to the first target row address, randomly select one of the row addresses as a second target row address, and perform a second refresh operation on at least one second address adjacent to the second target row address. The second refresh operation may be performed when the reference value flag signal indicates that the access count is not greater than the reference value.