Multi-level Program Pulse for Memory Cell Endurance
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Solution Overview
Problem
Programming in the single bit per cell (SLC) mode of memory devices causes significant damage to memory cells, leading to reduced endurance and an unfavorable ratio of SLC cycles to multiple bits per cell (MLC) cycles due to high initial program pulses that induce traps in the tunnel oxide layer.
Innovation Solution
Implementing a multi-level program pulse with an initial lower program level followed by a higher level, accompanied by a pass level to reduce the electric field stress, and adjusting voltages of adjacent word lines to minimize step-up time and damage, while optimizing program levels based on temperature, program-erase cycles, and sub-block position.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high initial program pulse is applied to program memory cells in SLC mode, then programming speed is improved, but damage to memory cells increases due to high electric field stress inducing traps in the tunnel oxide layer
Solution Approach 1:
The program pulse is divided into multiple levels: an initial lower program level followed by a higher program level. This segmentation allows the programming process to proceed in stages, reducing the peak electric field stress while still achieving effective programming, thus resolving the contradiction between programming speed and memory cell damage
Solution Approach 2:
A pass level is applied before the program pulse to preliminarily reduce the electric field stress on the tunnel oxide layer. This preliminary action prepares the memory cell for programming while minimizing damage, allowing subsequent program pulses to be applied more safely
2Reliability
If a multi-level program pulse with pass level is used to reduce damage, then memory cell endurance is improved, but programming complexity increases
Solution Approach 1:
The programming process uses periodic application of different voltage levels (pass level, lower program level, higher program level) in a defined sequence. This periodic action structure makes the complex multi-level programming process more manageable and systematic, reducing the perceived complexity while maintaining reliability benefits
Solution Approach 2:
The voltage parameters of the program pulse are dynamically adjusted based on temperature, program-erase cycle count, and sub-block position. This parameter adaptation optimizes the programming process for different operating conditions without requiring fundamentally different programming architectures, thus managing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the magnitude of Vpgm-Vth, minimizing damage to memory cells and enhancing the endurance of memory devices by optimizing the programming process.
Implementation Method 1
reduces the magnitude of Vpgm-Vth, minimizing damage to memory cells
Data Source
AI summary
Apparatuses and techniques are described for reducing damage to memory cells during single bit per cell programming. An initial program pulse in a single bit per cell program operation has a lower, first program level followed by a higher, second program level. As a result of the lower, first program level, the electric field across the memory cells is reduced. The step up time from the first program level to the second program level can be reduced by concurrently stepping up pass voltages of the adjacent unselected word lines. If an additional program pulse is applied, the step up in the program pulse can be omitted. The magnitude of the first program level can be adjusted based on factors such as temperature, number of program-erase cycles, selected sub-block position and selected word line position.