Row Hammer Refresh Address Control Circuit
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Solution Overview
Problem
Conventional solutions for detecting and mitigating the row hammer effect in DRAM devices are complex and require extensive circuitry, leading to inefficient data retention and corruption in densely packed memory cells.
Innovation Solution
A refresh address control circuit with a sampling signal generator and shift register that randomly samples row addresses to detect frequent access patterns, generating a match signal to trigger targeted refresh operations and reduce data loss by identifying and refreshing adjacent rows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional row hammer detection solutions are implemented, then data retention is improved, but device complexity increases due to extensive circuitry requirements
Solution Approach 1:
The refresh address control circuit automatically detects row hammer attacks and initiates refresh operations without external intervention. The circuit monitors access patterns to the same row address and autonomously determines when refresh is needed, making the system self-protecting against row hammer effects
Solution Approach 2:
The circuit performs preliminary detection of repeated row accesses and proactively initiates refresh operations before data corruption occurs. By detecting access patterns and triggering refresh in advance, the system prevents data loss rather than responding after corruption happens
2Measurement precision
If extensive circuitry is used for row hammer detection, then detection accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The refresh address control circuit serves multiple functions: it generates normal refresh addresses, detects row hammer attacks by monitoring access patterns, and initiates targeted refresh operations. This multi-functionality eliminates the need for separate dedicated detection circuitry, simplifying manufacturing while maintaining detection accuracy
Solution Approach 2:
The patent combines row hammer detection functionality with the existing refresh address control circuit. By merging detection and refresh operations into a single integrated circuit, the design avoids the need for separate extensive detection circuitry, reducing manufacturing complexity while preserving detection capabilities
Data Source
AI summary
An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.


