Semiconductor Memory Device Using Non-Volatile RRAM Cache
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Solution Overview
Problem
Conventional NAND-type flash memory page buffers, being volatile, face challenges such as increased area requirements, data loss upon power off, and limited continuous programming capabilities due to their CMOS latch circuit design, which hinders miniaturization and efficient data handling.
Innovation Solution
A semiconductor memory device incorporating a data maintaining system with both volatile and non-volatile memory elements, utilizing a resistance random access memory (RRAM) for the cache register to enable high-speed, flexible data reading and programming by maintaining data even when power is off and allowing for more flexible programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a volatile CMOS latch circuit is used for the page buffer, then the circuit can operate at high speed, but the area of the page buffer increases and data is lost when power is off
Solution Approach 1:
The patent changes the fundamental parameter of memory element type from volatile CMOS latch to non-volatile memory element, enabling data retention without power while using fewer transistors (4T vs conventional 6T latch), thus reducing area while maintaining operation capability
Solution Approach 2:
The page buffer is segmented into a non-volatile memory element for data storage and minimal supporting circuitry, separating the data retention function from the volatile latch circuit, allowing efficient use of space while maintaining high-speed operation when needed
2Device complexity
If a volatile CMOS latch circuit is used for the page buffer, then the circuit can be simple, but data is lost when power is off
Solution Approach 1:
The patent changes the parameter of volatility to non-volatility by using non-volatile memory elements, ensuring data is retained even when power is off, thus improving reliability without significantly increasing circuit complexity
Solution Approach 2:
The patent uses simple non-volatile memory elements that replace complex volatile latch circuits, achieving reliable data retention with simpler, more robust components that don't require continuous power to maintain state
3Productivity
If the same page is continuously programmed multiple times, then the utilization rate increases and programming time is reduced, but the word line high voltage application causes threshold value degradation of neighboring page memory cells
Solution Approach 1:
The non-volatile cache register acts as an intermediary buffer that stores program data before it is programmed to the memory array. This allows multiple programming operations to be prepared without repeatedly applying high voltage to the same word line, reducing threshold degradation of neighboring cells while maintaining high programming efficiency
Solution Approach 2:
The patent implements preliminary action by pre-loading program data into the non-volatile cache register before actual programming to the memory array. This allows multiple pages of data to be prepared in advance, reducing the frequency of high-voltage applications to the same word line and preventing threshold value degradation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed data handling and flexible programming operations by maintaining data with non-volatile RRAM, preventing data loss and allowing for continuous programming beyond conventional limits, thus enhancing the performance and efficiency of NAND-type flash memory.
Implementation Method 1
The cache register includes a non-volatile memory element, and more particularly, a resistance random access memory (RRAM)
Data Source
AI summary
A semiconductor memory device for high speed operation, and for flexible data reading and programming is disclosed. The flash memory of the present disclosure includes: a page buffer/sensor circuit including a volatile memory element that may maintain data with a size corresponding to a page of a memory array; a high speed cache register including a non-volatile memory element that may maintain data with a size corresponding to a page of a memory array. The page buffer/sensor circuit includes a sensor circuit, a data register, and a transmission gate. The data register may transmit and receive data with an input-output buffer. The high speed cache register includes RRAM, wherein the RRAM may transmit and receive data with an input-output buffer via a transmission gate, and may transmit and receive data with the data register via a transmission gate.