Memory Array Programming via Bit Line Floating and Ramp Signals
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Solution Overview
Problem
Conventional flash memory programming requires high operation voltage and gate-coupling ratio, leading to increased power consumption and variability in programming speed across memory cells.
Innovation Solution
A method for programming a memory array where the bit line is floated during the programming phase, reducing current flow through the memory cell string and ensuring all memory cells on different word lines have the same programming speed by utilizing a ramp signal and specific voltage applications across transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional FN tunneling effect programming is used, then programming capability is achieved, but power consumption increases due to higher operation voltage and gate-coupling ratio requirements
Solution Approach 1:
The patent changes the programming mechanism from FN tunneling effect to hot carrier injection, altering the physical parameters of the programming process. This enables programming at lower voltages and reduces the gate-coupling ratio requirement, directly addressing the power consumption issue while maintaining programming capability
Solution Approach 2:
The patent introduces dynamic voltage control through a ramp signal that gradually increases the word line voltage during programming. This dynamic approach allows the system to achieve the necessary programming effect with lower peak voltages compared to conventional static high-voltage programming, thereby reducing power consumption
2Reliability
If conventional programming with connected bit line is used, then programming speed varies across memory cells on different word lines, but floating bit line reduces programming speed uniformity
Solution Approach 1:
The patent applies preliminary voltage to the bit line before the ramp signal is applied to the word line. This preliminary action prepares the memory cell string in advance, ensuring that when programming occurs, all cells experience consistent conditions regardless of their position on different word lines, thereby improving programming speed consistency
Solution Approach 2:
The patent uses the bit line as an intermediary element that, when floated, isolates different memory cell strings from each other during programming. This prevents cross-interference between cells on different word lines and ensures uniform programming conditions, with the trade-off being increased control complexity for achieving reliable consistent programming
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and enhances the reliability and overall performance of the memory array by maintaining consistent programming speed across all memory cells.
Implementation Method 1
a ramp signal is provided to a word line electrically connected to the switching memory cell
Data Source
AI summary
A method for programming a memory array is provided. The memory array includes a memory cell string composed of a first transistor, a plurality of memory cells and a second transistor connected in series, and the method for programming the memory array includes following steps. In a setup phase, a switching memory cell in the memory cells is turned off, and a first voltage and a second voltage are applied to a first source/drain and a second source/drain of the switching memory cell. In a programming phase, a bit line connected to the memory cell string is floating, and a ramp signal is provided to a word line electrically connected to the switching memory cell.