Buried Source Line Protrusions for 3D Memory Arcing
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Solution Overview
Problem
As three-dimensional memory devices scale down, buried source line arcing occurs during anisotropic etch processes due to the accumulation of positive electrical charge in the buried source layer, which affects the manufacturing of three-dimensional memory devices.
Innovation Solution
The method involves forming a buried source line with a conductive material layer and a doped semiconductor layer, where the conductive material layer includes downward-protruding portions that are electrically shorted to the semiconductor substrate, providing a path for negative charge flow to neutralize positive charge accumulation in the alternating stack, thereby preventing arcing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the buried source line is formed as a continuous conductive layer across chip regions and scribe regions, then electrical connectivity is maintained, but positive charge accumulation occurs during anisotropic etch leading to arcing
Solution Approach 1:
The buried source line is segmented into distinct regions: continuous conductive portions within chip regions and downward-protruding conductive portions in scribe regions. This segmentation allows the line to maintain electrical connectivity while creating localized charge dissipation paths that prevent arcing during anisotropic etch processes.
Solution Approach 2:
The downward-protruding portions of the buried source line act as intermediary structures that provide a controlled path for negative charge flow. These protrusions extend into the alternating stack to neutralize positive charge accumulation, serving as a mediator between the substrate and the charge-prone regions, thereby preventing harmful arcing.
2Reliability
If the buried source line extends into scribe regions with downward-protruding portions, then charge neutralization is improved, but device complexity increases
Solution Approach 1:
The buried source line performs multiple functions: it provides electrical connectivity within chip regions, extends into scribe regions for charge neutralization, and maintains structural integrity across the entire substrate. This multi-functionality reduces the need for separate charge dissipation structures, thereby limiting the increase in device complexity.
Solution Approach 2:
The downward-protruding portions of the buried source line are formed in advance during the same processing steps that create the alternating stack. By preparing these charge-neutralization features beforehand, the patent avoids adding complex post-processing steps, thus limiting the increase in device complexity while ensuring effective charge neutralization.
3Manufacturing precision
If the conductive material layer is deposited as a blanket layer, then manufacturing precision is maintained, but charge accumulation in alternating stack occurs
Solution Approach 1:
While the conductive material layer is deposited uniformly as a blanket layer (maintaining manufacturing precision), the subsequent patterning process creates local variations: continuous layers in chip regions and downward-protruding portions in scribe regions. This local differentiation enables charge neutralization in specific areas without compromising the overall deposit uniformity.
Solution Approach 2:
The conductive material layer transitions from a two-dimensional blanket deposit to a three-dimensional structure with downward-protruding portions that extend into the alternating stack. This dimensional change allows the layer to access and neutralize charge in previously inaccessible regions while maintaining the simplicity of blanket deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates arcing between the buried source line and the substrate during anisotropic etch processes, ensuring reliable manufacturing of three-dimensional memory devices by neutralizing electrical charge and maintaining device integrity.
Implementation Method 1
the conductive material layer includes downward-protruding portions that are electrically shorted to the semiconductor substrate, providing a path for negative charge flow to neutralize positive charge accumulation in the alternating stack
Data Source
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AI summary
A method of forming a three-dimensional memory device includes forming at the least one lower level dielectric layer over a semiconductor substrate, forming a buried source line over the least one lower level dielectric layer and over the semiconductor substrate, such that the buried source line is electrically connected to the semiconductor substrate, forming an alternating stack of insulating layers and sacrificial material layers over the buried source line, such that the sacrificial material layers are subsequently replaced with, electrically conductive layers, forming memory openings through the alternating stack by etching through the alternating stack after the buried source line is electrically connected to the semiconductor substrate, and forming memory stack structures in the memory openings. Each memory stack structure includes a vertical semiconductor channel electrically connected to the buried source line and a memory film laterally surrounding the vertical semiconductor channel.