Skew Signal Generator for Semiconductor Memory Delay Adjustment
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Solution Overview
Problem
As semiconductor devices are scaled down, property variations in transistor performance due to skew states (SLOW, TYPICAL, and FAST) lead to increased errors in manufacturing processes, making it difficult to control device variables like gate width, gate oxide thickness, and sheet resistance, which limits the applicability of skew adjustments to all internal circuits in semiconductor memory devices.
Innovation Solution
A skew signal generator that encodes fuse signals into skew signals (SLOW, TYPICAL, and FAST) to adjust delay intervals in a semiconductor memory device's delay circuit, allowing for dynamic voltage adjustments based on skew information obtained from wafer tests, thereby reducing internal circuit variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor devices are scaled down to reduce size, then device miniaturization is achieved, but property variation in transistor performance increases due to manufacturing process errors
Solution Approach 1:
The patent applies preliminary action by performing wafer-level skew testing and fuse cutting before final device assembly. The skew state is determined early in the manufacturing process, and compensatory fuse configurations are established beforehand to pre-compensate for detected performance variations, thereby reducing the impact of manufacturing precision limitations on final device performance.
Solution Approach 2:
The patent changes physical parameters by selectively cutting fuses to alter the reference voltage level based on detected skew states. This parameter adjustment compensates for transistor performance variations caused by scaling, allowing devices with different manufacturing characteristics to operate within specified performance ranges despite the inherent increase in property variation.
2Reliability
If fuse cutting is performed individually for each internal circuit based on skew, then circuit-specific skew compensation is achieved, but the applicability of skew adjustment to all internal circuits is limited
Solution Approach 1:
The patent achieves universality by implementing a common skew detection and compensation mechanism that serves all internal circuits simultaneously. The wafer-level skew test and fuse configuration establish a global compensation strategy that applies across multiple circuits, allowing the same reference voltage adjustment to benefit various internal circuits rather than requiring individual circuit-specific adjustments.
Data Source
AI summary
A skew signal generator is provided which comprises a fuse signal generating unit for generating a plurality of fuse signals, and an encoder for generating skew signals including skew information of a wafer by encoding the fuse signals.