Multi-deck Memory Device with Under-Array Buffer Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional single-deck memory devices face challenges in improving performance and size due to limitations in access and data line management, leading to inefficiencies in read, write, and erase operations.
Innovation Solution
A memory device with multiple decks of memory cells, featuring separate page buffer circuitry for each deck, distinct driver circuits, and electrically separate data lines, allowing concurrent access and operation across decks with shared access lines, enhancing operational efficiency and reducing the number of driver circuits needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate driver circuits are provided for each deck, then each deck can be independently controlled, but the number of driver circuits increases and device complexity increases
Solution Approach 1:
A single driver circuit is designed to serve multiple decks by implementing multi-functional capabilities. The driver circuit can selectively connect to and control different decks through switching mechanisms, allowing one driver circuit to perform the functions of multiple dedicated driver circuits, thereby reducing overall device complexity while maintaining independent deck control capability
Solution Approach 2:
The driver circuit incorporates dynamic switching mechanisms that allow it to adaptively connect to different decks based on operational requirements. This dynamic reconfiguration enables a single driver circuit to serve multiple decks sequentially or concurrently, providing flexibility and adaptability without requiring separate static driver circuits for each deck
2Productivity
If multiple decks operate concurrently, then operational efficiency improves, but access line management becomes more complex
Solution Approach 1:
Access lines are segmented and organized into distinct groups, with each group associated with specific decks. This segmentation allows for systematic management of access lines during concurrent operations, reducing the complexity of routing and controlling signals to multiple decks simultaneously while enabling parallel access to different memory regions
3Area of stationary object
If buffer circuitry is shared across decks, then device size is reduced, but access conflicts may occur between decks
Solution Approach 1:
Control logic acts as an intermediary between multiple decks and the shared buffer circuitry. This intermediary manages access requests from different decks, arbitrating conflicts and coordinating buffer usage to ensure reliable operation. The control logic enables multiple decks to share buffer resources without conflicts by implementing proper access protocols and timing control
Data Source
AI summary
Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a substrate, a first deck including first memory cell strings located over the substrate, a second deck including second memory cell strings and located over the first deck, first data lines located between the first and second decks and coupled to the first memory cell strings, second data lines located over the second deck and coupled to the second memory cell strings, and first and second circuitries. The first and second data lines extending in a direction from a first portion of the substrate to a second portion of the substrate. The first buffer circuitry is located in the first portion of the substrate under the first memory cell strings of the first deck and coupled to the first data lines. The second buffer circuitry is located in the second portion of the substrate under the first memory cell strings of the first deck and coupled to the second data lines.