Bitline Boost Timing for NAND Flash Memory
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Solution Overview
Problem
In NAND flash memory devices, the strong capacitive coupling between inhibit and program bit lines leads to RC delays, which slows down programming performance and can result in reliability issues such as program disturb, especially in QLC technology where strong boosting is required to prevent program disturb for certain word lines while maintaining speed for others.
Innovation Solution
The method involves delaying the program bit line boost for a second precharge time period to account for the RC delay on the inhibit bit line, allowing the inhibit bit line to charge to a higher level before boosting, using capacitive coupling between adjacent bit lines, and employing detection circuitry to ensure the inhibit bit line reaches the necessary voltage level before boosting, thereby overcoming RC delays and improving program disturb resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the program bit line is boosted immediately during programming, then programming speed is improved, but RC delays on the inhibit bit line cause program disturb and reliability issues
Solution Approach 1:
The patent applies preliminary action by pre-charging the inhibit bit line to a high voltage level (e.g., VDD or VSS) before the program bit line boost occurs. This preliminary charging of the inhibit bit line, performed through current sources connected to bit line terminals, ensures that the inhibit line is ready to prevent program disturb before the actual programming action takes place. The detection circuitry monitors this pre-charge process to ensure the inhibit bit line reaches the necessary voltage level before boosting the program bit line.
2Reliability
If the inhibit bit line is charged faster to overcome RC delays, then program disturb resistance is improved, but detection precision and timing control become more difficult
Solution Approach 1:
The patent implements feedback through detection circuitry that continuously monitors the voltage level on the inhibit bit line. This detection circuitry provides feedback information about the charging status of the inhibit bit line to the control logic. Based on this feedback, the system can determine when the inhibit bit line has reached the required voltage level before proceeding with the program bit line boost. This feedback mechanism ensures precise timing control and accurate voltage level detection, resolving the contradiction between fast charging and measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming speed while maintaining reliability by ensuring the inhibit bit line reaches the required voltage level before boosting, reducing program disturb and improving overall programming performance.
Implementation Method 1
delaying program bit line boost for a second precharge time period while continuing to drive the inhibit bit line to account for a resistance-capacitance (RC) delay on the inhibit bit line
Data Source
AI summary
A methodology and structure for a bit line boost during a programming operation in a nonvolatile memory are described. The inhibit bit line is driven for a first precharge time period with a constant current. The program bit line boost is delayed for a second precharge time period while continuing to drive the inhibit bit line to account for a resistance-capacitance (RC) delay on the inhibit bit line. Thereafter, the program bit line is boosted at the end of the second time period to a program voltage level. The signal level at the fare end of the bit line remote from the driven end of the bit line is sensed to determine when the inhibit bit line reaches a level (e.g. VDDSA) or a level at which the current limits are turned off. Thereafter, the bit line boost can be performed.