Shared Block Decoder for Defective Memory Cell Management
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Solution Overview
Problem
The manufacturing cost of memory devices is high due to complex decoder circuits with a large number of elements and wirings required for managing defective memory cell groups in three-dimensional NAND flash memory systems.
Innovation Solution
A memory device configuration with a shared block decoder that uses a reduced number of elements and wirings by incorporating a signal retention circuit and a determination circuit to manage defective memory cell groups, allowing for efficient selection and deselection of memory cell groups based on bad block information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a complex decoder circuit with a large number of elements and wirings is used to manage defective memory cell groups, then the reliability of defect management is improved, but the manufacturing cost increases
Solution Approach 1:
The decoder circuit is segmented into a normal block decoder and a bad block decoder that operate independently. The bad block decoder is further divided into a determination circuit and a signal retention circuit. This segmentation allows each component to have a specialized, simplified function, reducing overall complexity while maintaining comprehensive defect management capability.
Solution Approach 2:
The defect management function is extracted from the normal decoder operation and implemented as a separate bad block decoder. This extraction allows the normal decoder to focus on standard decoding operations while the bad block decoder handles defect management, reducing the complexity burden on the main decoding path.
2Adaptability or versatility
If a complex decoder circuit with many elements and wirings is used, then the capability to manage defective memory cell groups is improved, but the device complexity increases
Solution Approach 1:
The decoder is divided into functionally independent segments: normal block decoder for standard operations and bad block decoder for defect management. The bad block decoder is further segmented into determination circuit (for assessing defect status) and signal retention circuit (for maintaining defect information). This segmentation reduces inter-component complexity while preserving comprehensive defect management capability.
Solution Approach 2:
The bad block decoder is designed to universally handle defect management across all memory blocks through standardized determination and signal retention functions. This multi-functional design allows a single specialized circuit to manage defects throughout the entire memory array, reducing the need for multiple separate defect management circuits.
3Ease of manufacture
If a simplified decoder circuit with fewer elements and wirings is used, then the manufacturing cost is reduced, but the ability to manage defective memory cell groups may be compromised
Solution Approach 1:
By segmenting the decoder into normal and bad block decoders with specialized functions, each component can be optimized for its specific task with minimal necessary elements. The determination circuit uses only the elements needed to assess block status, and the signal retention circuit uses only what's needed to maintain defect information, reducing total element count while preserving reliability.
Solution Approach 2:
The bad block decoder acts as an intermediary between the normal decoder and the memory cell groups, filtering and managing defect information separately. This intermediary structure allows defect management to be handled through a dedicated simplified path, maintaining reliability without requiring the normal decoder to be overly complex.
Data Source
AI summary
A memory device includes a memory cell array including a plurality of memory cell groups, and a decoder circuit configured to control selection of the memory cell groups. The decoder circuit includes an address decoder circuit configured to activate the decoder circuit based on an input address, a plurality of information retention circuits, each of which corresponds to one of the memory cell groups and outputting a signal that indicates whether or not the corresponding memory cell group is defective, a transistor having a gate connected to each of the outputs of the information retention circuits, and a signal output circuit configured to output a control signal for selecting or not selecting the memory cell groups based on an on/off state of the transistor.