X-DRAM Memory Array Sub-Array Multiplexing
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Solution Overview
Problem
Existing memory devices face issues such as high latency, low data throughput, and high power consumption, which hinder the performance and efficiency of industrial and consumer electronics.
Innovation Solution
The X-DRAM (X-RAM) technology introduces a novel memory array architecture that reduces the size of the sense amplifier circuit, allowing for increased speed and reduced power consumption by dividing the memory array into sub-arrays and using bit line select gates to multiplex multiple bit lines to a single sense amplifier, thereby minimizing the number of sense amplifiers and die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory array architecture is used, then sufficient sense amplifiers are available to handle all bit lines, but the die size becomes large and power consumption increases
Solution Approach 1:
The memory array is divided into multiple sub-arrays, each handling a portion of the bit lines. This segmentation allows the sense amplifier to serve multiple sub-arrays sequentially rather than requiring dedicated sense amplifiers for all bit lines simultaneously, reducing the total number of sense amplifiers needed and thereby reducing die size.
Solution Approach 2:
The system dynamically switches between different sub-arrays using bit line select gates. The sense amplifier is dynamically allocated to different sub-arrays based on access patterns, allowing one sense amplifier to serve multiple sub-arrays over time. This dynamic sharing reduces the number of sense amplifiers required while maintaining full functionality.
2Productivity
If conventional memory array architecture is used, then all bit lines can be accessed simultaneously, but power consumption becomes high
Solution Approach 1:
The bit lines are divided into groups associated with different sub-arrays. Only the sub-array currently being accessed is activated, meaning only a subset of bit lines is active at any given time. This segmentation reduces the number of simultaneously active bit lines, thereby reducing power consumption while maintaining overall data throughput through sequential access.
Solution Approach 2:
The system uses periodic switching between different sub-arrays via bit line select gates. Each sub-array is activated in sequence, allowing the sense amplifier to service multiple sub-arrays over time. This periodic activation reduces instantaneous power consumption compared to having all bit lines active simultaneously, while maintaining aggregate data throughput.
3Speed
If more sense amplifiers are used to handle all bit lines, then access speed is improved, but die size and manufacturing complexity increase
Solution Approach 1:
The sense amplifier is designed to be universal, capable of servicing multiple sub-arrays through the bit line select gates. Instead of having dedicated sense amplifiers for each bit line or sub-array, a single sense amplifier performs multiple functions by sequentially accessing different sub-arrays. This multi-functionality reduces the total number of sense amplifiers needed while maintaining access speed performance.
Solution Approach 2:
Bit line select gates are introduced as intermediary components between the sense amplifier and multiple sub-arrays. These select gates enable the sense amplifier to efficiently switch between different sub-arrays without requiring direct connections to all bit lines. This intermediary mechanism simplifies the overall architecture by reducing the number of sense amplifiers while maintaining fast access through controlled switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in significantly reduced latency, increased data throughput, and lower power consumption, enhancing the performance and efficiency of memory operations while maintaining a comparable or smaller die size compared to conventional architectures.
Implementation Method 1
deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line
Data Source
AI summary
Methods and apparatus for a novel memory array are disclosed. In an embodiment, a method is provided for reading a dynamic random-access memory (DRAM) array. The method includes activating the bit line select gates to equalize voltage levels on a plurality of bit lines, deactivating the bit line select gates to maintain the equalized voltage levels on the plurality of bit lines using a bit line capacitance associated with each bit line, and activating a selected word line to access selected memory cells connected to the selected word line. The method also includes activating bit line select gates to pass first data from a first bit line and second data from a second bit line to the sense amplifier. The first data is from a selected memory cell and the second data is reference data. The method also includes determining sensed data from the first and second data.