Shared Column Decoder for Semiconductor Memory Bank Integration
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving higher integration and reducing power consumption due to the large circuit area occupied by data input circuits, which increases with the number of memory banks.
Innovation Solution
The semiconductor memory device integrates multiple memory bank units with shared column decoders and a control signal generation circuit to reduce the size of the data input circuit, allowing for a single counter to generate column addresses and control data latch operations across memory banks, thereby simplifying the circuit configuration and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory banks are added to increase storage capacity, then the storage capacity is improved, but the circuit area occupied by data input circuits increases
Solution Approach 1:
The patent merges the data input circuits of multiple memory banks into a single shared circuit. Instead of providing separate data input circuits for each memory bank, the invention uses one common data input circuit that serves all memory banks, thereby reducing the total circuit area while maintaining the ability to handle data for multiple banks.
Solution Approach 2:
The shared data input circuit is designed to be universal, capable of handling data input operations for any of the multiple memory banks. The circuit can be dynamically configured to serve different banks as needed, making a single circuit perform the function of what would traditionally require multiple separate circuits.
2Quantity of substance
If multiple memory banks are added to increase storage capacity, then the storage capacity is improved, but the power consumption increases
Solution Approach 1:
The patent combines the control logic for data input operations into a single control circuit that manages all memory banks. This eliminates the need for multiple separate control circuits, reducing the number of active components and thereby lowering overall power consumption while still supporting multiple memory banks.
Solution Approach 2:
The universal control circuit can selectively activate data input operations for specific memory banks based on operational needs. This allows the system to power down or idle unused portions of the circuit, reducing power consumption compared to having permanently active separate circuits for each bank.
3Reliability
If separate data input circuits are provided for each memory bank, then the data input operation reliability is improved, but the device complexity increases
Solution Approach 1:
The patent segments the control functionality into distinct control signals that can selectively target specific memory banks. The shared data input circuit responds to bank-specific control signals, allowing reliable operation for each bank while maintaining a unified circuit structure. This segmentation of control logic enables the single circuit to reliably serve multiple banks without the complexity of multiple independent circuits.
Data Source
AI summary
A semiconductor memory device includes a first page buffer block and a second page buffer block corresponding to a first memory bank and a second memory bank, respectively, an input/output control circuit suitable for transferring input data to data lines, a first column decoder and a second column decoder suitable for latching the input data transferred through the data lines to the first page buffer block and the second page buffer block, respectively, based on a column address transferred through address lines that are shared by the first and second column decoders, and a control signal generation circuit suitable for generating a plurality of page buffer selection signals to control the first and second column decoders to selectively perform data latch operations on the first and second page buffer blocks.