Memory Controller Parallel Shift Read Voltage Optimization
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Solution Overview
Problem
Current memory systems face challenges in efficiently adjusting read voltages to accurately retrieve data due to variations in threshold voltages of memory cells, leading to errors and increased time required for data retrieval.
Innovation Solution
A memory system with multiple planes, where each plane executes shift read operations in parallel using different read voltages, allowing the memory controller to optimize voltage levels based on data read from multiple planes, thereby reducing the time needed to adjust read voltages and improve data accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read voltage adjustment is performed sequentially on single planes, then voltage optimization accuracy is improved, but data retrieval time increases
Solution Approach 1:
The memory system is divided into multiple independent planes, each capable of performing shift read operations independently. This segmentation allows parallel processing of voltage adjustment across different planes, reducing overall adjustment time while maintaining optimization accuracy for each plane's read operations
Solution Approach 2:
Multiple planes perform shift read operations continuously in parallel, eliminating idle time between sequential adjustments. The memory controller coordinates simultaneous voltage adjustments across planes, ensuring continuous useful action without sacrificing the precision needed for accurate read operations
2Productivity
If multiple planes perform shift read operations in parallel, then data retrieval time is reduced, but voltage adjustment complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle parallel voltage adjustment across multiple planes simultaneously. It can issue shift read commands to different planes with different voltage offsets in parallel, managing the complexity through a unified control mechanism that coordinates all planes' operations
Solution Approach 2:
The system pre-establishes voltage offset values for multiple planes before parallel operations begin. This preliminary preparation of voltage adjustment parameters allows the memory controller to execute parallel shift read operations without real-time calculation overhead, reducing operational complexity while maintaining high data retrieval speed
3Device complexity
If threshold voltage variations are not compensated, then system simplicity is maintained, but data accuracy deteriorates
Solution Approach 1:
The memory system performs self-diagnosis through shift read operations, automatically detecting threshold voltage variations and adjusting read voltages accordingly. This self-service mechanism compensates for voltage drift without external intervention, maintaining data accuracy while adding minimal system complexity through automated feedback loops
Data Source
AI summary
A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.